A method of manufacturing a display device including: preparing a substrate having a display area and a non-display area; and forming an alignment mark disposed in the non-display area of the substrate. The alignment mark includes a quadrangular-shaped center portion and a plurality of measurement portions that surround the center portion, the plurality of measurement portions including four or more measurement portions, and each of the measurement portions including sides that are parallel with two sides of the quadrangular-shaped center portion.

A method for selecting an optimal set of locations for a measurement or feature on a substrate, the method includes: defining a first candidate solution of locations, defining a second candidate solution with locations based on modification of a coordinate in a solution domain of the first candidate solution, and selecting the first and/or second candidate solution as the optimal solution according to a constraint associated with the substrate.

A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

Methods and apparatuses for determining a position of an alignment mark applied to a region of a first layer on a substrate using a lithographic process by: obtaining an expected position of the alignment mark; obtaining a geometrical deformation of the region due to a control action correcting the lithographic process; obtaining a translation of the alignment mark due to the geometrical deformation; and determining the position of the alignment mark based on the expected position and the translation.

A sensor apparatus (300) for determining a position of a target (330) of a substrate (W) comprising, projection optics (315;321) configured to project a radiation beam (310) onto the substrate, collection optics (321) configured to collect measurement radiation (325) that has scattered from the target, a wavefront sensing system (335) configured to determine a pupil function variation of at least a portion (355) of the measurement radiation and output a signal (340) indicative thereof, and a measurement system (350) configured to receive the signal and to determine the position of the target in at least partial dependence on the collected measurement radiation and the determined pupil function variation of at least a portion of the measurement radiation.

Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.

A method includes forming a first photomask including N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions, forming a second photomask including M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions, performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer. The first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M is two times N.

A method for selecting an optimal set of locations for a measurement or feature on a substrate, the method includes: defining a first candidate solution of locations, defining a second candidate solution with locations based on modification of a coordinate in a solution domain of the first candidate solution, and selecting the first and/or second candidate solution as the optimal solution according to a constraint associated with the substrate.

Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

A method of processing a wafer is provided. The method includes providing a reference plate below the wafer. The reference plate includes a reference pattern. The reference plate is imaged to capture an image of the reference pattern by directing light through the wafer. A first pattern is aligned using the image of the reference pattern. The first pattern is applied to a working surface of the wafer based on the aligning.