An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

A detection device is connected to a plurality of communication devices by a communication line. The detection device has a reception unit, a measurement unit, and a detection unit. The reception unit receives signals with prescribed pulse widths transmitted from the plurality of communication devices, respectively. The measurement unit measures the pulse widths of the signals received by the reception unit. The detection unit is configured to detect the communication device disposed near a terminal end of the communication line as a terminal-end communication device on the basis of the plurality of pulse widths measured by the measurement unit.

A detection device is connected to a plurality of communication devices by a communication line. The detection device has a reception unit, a measurement unit, and a detection unit. The reception unit receives signals with prescribed pulse widths transmitted from the plurality of communication devices, respectively. The measurement unit measures the pulse widths of the signals received by the reception unit. The detection unit is configured to detect the communication device disposed near a terminal end of the communication line as a terminal-end communication device on the basis of the plurality of pulse widths measured by the measurement unit.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

A multi-power distributed storage system including a first power source; a second power source electrically connected to a common bus with the first power source; a single input port inverter electrically connected to the common bus. The system including a controller configured to communicate with at least the second power source, and the single input port inverter. The second power source including a plurality of battery banks and a plurality of bi-directional DC/DC converters configured to charge and discharge the plurality of battery banks and provide DC to the single input port inverter.

A multi-power distributed storage system including a first power source; a second power source electrically connected to a common bus with the first power source; a single input port inverter electrically connected to the common bus. The system including a controller configured to communicate with at least the second power source, and the single input port inverter. The second power source including a plurality of battery banks and a plurality of bi-directional DC/DC converters configured to charge and discharge the plurality of battery banks and provide DC to the single input port inverter.

A control apparatus characterized by including: a storage unit that stores operation management information; an application executing unit that transmits a signal for turning off the power source of a field instrument; a resetting unit that, based on the signal, instructs to suspend the power supply from the input/output modules; and an activating unit that instructs to resume the power supply from the input/output modules, based on an elapse of preset time during which the power supply from the input/output modules should be suspended.

A control apparatus characterized by including: a storage unit that stores operation management information; an application executing unit that transmits a signal for turning off the power source of a field instrument; a resetting unit that, based on the signal, instructs to suspend the power supply from the input/output modules; and an activating unit that instructs to resume the power supply from the input/output modules, based on an elapse of preset time during which the power supply from the input/output modules should be suspended.