A multi-logic device system, an electronic engine controller, and a method of operating the multi-logic device system. The multi-logic device system includes a primary logic device which is more resilient to single event effects, and one or more secondary logic devices, each secondary logic device being powered by a respective power supply unit and being more susceptible to single event effects. The primary logic device is configured to run, for each secondary logic device, a respective watchdog timer. Each watchdog timer is restarted upon receipt of a restart signal from the respective secondary logic device. The primary logic device is also configured, in response to a watchdog timer timing out, to identify and reset the secondary logic device corresponding to the timed out watchdog timer.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

An industrial controller that integrates execution of a control program on the industrial controller with execution of additional functions on an external processing device is disclosed. Integrating the external processing device provides an improved system for third party development of control functions which may be unique to specific applications. The system manages communication between the industrial controller and the external processing device, manages access to data stored in the industrial controller, and makes the details of the integration transparent to the programmer.

An industrial controller that integrates execution of a control program on the industrial controller with execution of additional functions on an external processing device is disclosed. Integrating the external processing device provides an improved system for third party development of control functions which may be unique to specific applications. The system manages communication between the industrial controller and the external processing device, manages access to data stored in the industrial controller, and makes the details of the integration transparent to the programmer.

An adaptive process control system and corresponding method for independent steering of plant control systems is provided, wherein a plant associated with the plant control system includes a plurality of interlocked elements of one or more operational unit of the plant. The operation of an operational unit is controlled by the plant control system by means of the elements interlocked to the plant control system, wherein the adaptive, independent process control system is accessible by a plant process engine including a plant controller unit connected via the supervisory control and data acquisition unit with at least one programmable logic controller of the plant control system. The operation of the plant and the operational units is controlled by means of the programmable logic controller and the plurality of interlocked elements.

An adaptive process control system and corresponding method for independent steering of plant control systems is provided, wherein a plant associated with the plant control system includes a plurality of interlocked elements of one or more operational unit of the plant. The operation of an operational unit is controlled by the plant control system by means of the elements interlocked to the plant control system, wherein the adaptive, independent process control system is accessible by a plant process engine including a plant controller unit connected via the supervisory control and data acquisition unit with at least one programmable logic controller of the plant control system. The operation of the plant and the operational units is controlled by means of the programmable logic controller and the plurality of interlocked elements.

A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.