Machine logic (for example, software) for managing the nuisance level characteristic (for example, nuisance-level sound) of another user's electronic, media-connected device. The machine logic considers contextual information (such as where the user is presently located and whether it is appropriate for the user's device to be emanating a loud, nuisance level volume).

An apparatus that searches for a pattern in a signal is disclosed. The apparatus can be used to implement a real time trigger in an instrument such as a high speed oscilloscope. The apparatus includes a symbol generator and a finite state machine (FSM). The symbol generator receives an ordered sequence of signal values and converts the ordered sequence of signal values into an ordered sequence of symbols, each symbol having a plurality of states. The FSM receives the ordered sequence of symbols and generates a match signal if the ordered sequence of symbols includes a target sequence specified by a regular expression that includes a counting limitation on one of the symbol states. The FSM includes a counting state that includes a counter that counts instances of the one of the symbol states.

A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

A method includes emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board. Emulating the EAM-R system includes detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated with the secondary EAM-R board. The EAM-R system is emulated in an emulation system that includes at least one network connection. The emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board.

A method includes emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board. Emulating the EAM-R system includes detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated with the secondary EAM-R board. The EAM-R system is emulated in an emulation system that includes at least one network connection. The emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board.

An apparatus and method for establishing triggers for the opening of one or multiple gates to a mold cavity of an injection molding system, followed by a sequence of predetermined valve pin movements over the course on an injection cycle. In one embodiment, the invention provides a graphical user interface and control system enabling a user to select from and arrange a plurality of virtual icons into a user-defined virtual sequence that define associated triggering events and actuator controlled pin movements over the course of an injection cycle. In various embodiments, the apparatus and method allows the system operator to view a simulated profile of such triggers and movements and to compare the simulated profile to an actual profile to access differences and make adjustments to the triggers and sequencing more quickly and efficiently. This is particularly useful in sequential molding systems where multiple gates need to be programmed and adjusted to compensate for variations from a predetermined sequence.

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.