Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.