A method of operating a measurement instrument, such as a digital oscilloscope, includes receiving multiple analog input signals from a measurement target over respective channels, converting the analog input signal on each channel into a respective digital signal, and comparing signal values of the digital signal on each channel to at least one threshold to generate a stream of levels for each channel. The method includes combining the stream of levels for each channel into a combined stream of levels that reflects combined features of the multiple analog input signals, detecting a pattern in the combined stream of levels using a combined-feature matching procedure implemented by hardware, such as a Finite State Machine (FSM), and triggering the measurement instrument according to a result of the combined-feature matching procedure.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Methods and apparatus for disaggregation of semiconductor dies in an integrated circuit package. An example apparatus includes interface circuitry, machine readable instructions, programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate an adjacency matrix for different functional blocks to be implemented in an integrated circuit, the adjacency matrix defining connections between ones of the functional blocks, and determine a group of the functional blocks to be included in a first chiplet of a plurality of chiplets for the integrated circuit, the group of the functional blocks determined based on weights assigned to the connections defined in the adjacency matrix.

Methods and apparatus for disaggregation of semiconductor dies in an integrated circuit package. An example apparatus includes interface circuitry, machine readable instructions, programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate an adjacency matrix for different functional blocks to be implemented in an integrated circuit, the adjacency matrix defining connections between ones of the functional blocks, and determine a group of the functional blocks to be included in a first chiplet of a plurality of chiplets for the integrated circuit, the group of the functional blocks determined based on weights assigned to the connections defined in the adjacency matrix.

A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

Disclosed is a system for responsive daylight control using an electronically actuated shading device. Optionally, the system has a longer response time in opening the shading than in closing the shading. Optionally, the system inhibits opening of the shading device in the presence of a fluctuation in the daylight level. Optionally, the response time in opening the shading is increased when the system is powered by a battery and/or with decreasing battery charge.

Disclosed is a system for responsive daylight control using an electronically actuated shading device. Optionally, the system has a longer response time in opening the shading than in closing the shading. Optionally, the system inhibits opening of the shading device in the presence of a fluctuation in the daylight level. Optionally, the response time in opening the shading is increased when the system is powered by a battery and/or with decreasing battery charge.

A system is provided, which manages, by a microcontroller internal to a fan installed in a server, power data associated with the fan, wherein the fan includes two pins configured to communicate signals based on an inter-integrated circuit (I2C). During operation of the fan, the microcontroller measures a first and second amount of power consumed by the fan at a first and second time. The microcontroller transmits, via the two pins, the information to a system management entity which monitors and manages the server, wherein the system management entity controls a speed of the fan in response to receiving the measured power data and based on a net power comprising a difference between a total amount of power consumed by the server and an amount of power consumed by the fan.