An intelligent control system for a detector comprises an external control module (110) and at least one group of data transmission and control modules (120), wherein the external control module (110) is used for controlling packet issuing and feedback message processing; a fifth interface (125) connected to the external control module (110) and used for packet transmission; a processing unit (128); at least one group of first type of interfaces (121) respectively connected to a detector (150) and used for transmitting a control packet of the detector (150); at least one group of second type of interfaces (122) respectively connected to the detector (150) and used for transmitting original data of the detector (150); a data pre-processing unit (129) for acquiring and forwarding the original data or pre-processing data of the detector (150); and a sixth interface (126) connected to the external control module (110) and used for transmitting the original data/pre-processing data of the detector (150). The intelligent control system for a detector can form an intellectualized control platform for performing dynamic configuration, intelligent monitoring, power supply management, data processing, foreign interaction, firmware updating on the detector (150).

Embodiments of the present disclosure provide a method and an apparatus for resource management in an edge cloud. The method comprises obtaining information on at least one of the following: resource occupation of a reconfigurable functional unit associated with hardware accelerator resources or GPP resources, power consumption of a hardware accelerator associated with hardware accelerator resources, and power consumption of a server associated with GPP resources; and performing processing on the reconfigurable functional unit based on the obtained information, the processing including at least one of configuration, reconfiguration, and migration. The method and apparatus of the embodiments of the present disclosure increase efficiency of resource management of the edge cloud, lower system energy consumption, and/or enable more efficient virtualization mechanisms for hardware accelerator resources.

To collect highly accurately filter-processed data. Sensor signals are acquired from sensors in predetermined data acquisition periods, a filtering process is performed on the sensor signals, time series data generated by extracting some of the filtered sensor signals is transmitted to an external device in a predetermined data transmission period that is longer than the data acquisition period, and the data transmission period is synchronized with a communication period of the external device.

A method of operating a refinery including at least one coke drum coupled to a coker fractionator. A pump characteristics curve is provided for a fractionator bottom pump coupled to the coker fractionator comprising a net positive suction head required (NPSHr) curve as a function of a pump flow rate. Fog computing utilizes the pump characteristics curve along with at least one sensed input parameter including a real-time value for the pump flow rate to control the fractionator bottom pump to dynamically control a column pressure (Pc) in the coker fractionator. A reduction in Pc is obtained that reduces an available NPSH (NPSHa) which lessens a difference between the NPSHa and the NPSHr.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

A method of operating a refinery including at least one coke drum coupled to a coker fractionator. A pump characteristics curve is provided for a fractionator bottom pump coupled to the coker fractionator comprising a net positive suction head required (NPSHr) curve as a function of a pump flow rate. Fog computing utilizes the pump characteristics curve along with at least one sensed input parameter including a real-time value for the pump flow rate to control the fractionator bottom pump to dynamically control a column pressure (Pc) in the coker fractionator. A reduction in Pc is obtained that reduces an available NPSH (NPSHa) which lessens a difference between the NPSHa and the NPSHr.

Described herein are various technologies for monitoring the backplane of a control system and detecting modifications of the control system (e.g., removal of modules, firmware updates, etc.). A monitoring device includes a field programmable gate array (FPGA), and is connected to the backplane of the control system. The monitoring device receives signals, by way of the backplane, that are communicated among modules connected to the backplane. The monitoring device detects a modification to the control system based upon the received signals.

To collect highly accurately filter-processed data. Sensor signals are acquired from sensors in predetermined data acquisition periods, a filtering process is performed on the sensor signals, time series data generated by extracting some of the filtered sensor signals is transmitted to an external device in a predetermined data transmission period that is longer than the data acquisition period, and the data transmission period is synchronized with a communication period of the external device.