In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.

The invention realizes miniaturization, high performance, and informatization of a control device. Only an application not required to be repeatedly executed with respect to a control subject at an execution interval less than or equal to a prescribed time interval is assigned to a fourth core (114) of a PLC (10).

A method for processing data on a programmable logic controller includes a priority with a predetermined priority level assigned to at least one parallel processing section of a program of a master-processor core of a control task. Respective priority levels are inserted into a data structure as the respective master-processor core arrives at the parallel processing section. A parallel-processor core examines whether entries are present in the data structure and processes partial tasks from a work package of the master-processor core the priority level of which ranks first among the entries. A real-time condition of the control task is met by setting executing times of the programs for the master-processor core so that the master-processor core is capable of processing the partial tasks from the work packages without being supported by the parallel-processor core. The master-processor core further processes partial tasks not processed by the at least one parallel-processor core.

Provided is a control apparatus that can, by causing multiple control programs that include motion computation programs to be executed in parallel, shorten the execution cycle of control programs that are executed cyclically. A microprocessor is configured to execute multiple control programs in parallel. When executing communication commands included in control programs that are to be executed in parallel, a scheduling program causes the microprocessor to execute the communication commands such that there is no competition between communication processes in a communication controller.

The present disclosure meets demand to realize control computations according to programs having different execution formats by a single control device. The control device includes a storage unit storing a first program to be scanned as a whole for each execution and a second program that is sequentially executed, an execution processing unit computing a first command value by executing the first program at every predetermined control cycle, an interpreter interpreting at least a part of the second program and generating an intermediate code, a command value computation unit computing a second command value at every control cycle according to the intermediate code generated in advance by the interpreter, and an output unit outputting the first command value computed by the execution processing unit and the second command value computed by the command value computation unit at every control cycle.

A controller enables execution of control programs in parallel using a multi-core processor in shorter cycles without causing communication collisions. The controller executes control programs in multiple cycles. In accordance with the priorities assigned to a control program 1 and a control program 2, the controller controls the timing to execute communication associated with the control program 2 without colliding with communication with external devices associated with the control program 1.

An intelligent digital controller of a flexible material cutting robot and a realization method are provided. The controller comprises: an ARM chip, a servo driver bus communication module and a CPLD module. The ARM chip has built-in two processor cores (Cortex-M0 and Cortex-M4) and is externally connected with a flash memory, an SD card, SRAMs and an Ethernet physical transceiver_2; the Cortex-M0 reads a corresponding graph in the SD card into SRAM_1 according to a graph number, and sends a graph data readiness interruption request to an interruption controller; and after the interruption request is responded, Cortex-M4 reads in graph data and conducts interpolation calculation on the graph; the servo driver bus communication module is used to receive an interpolation calculation result and transmit the calculation result to a data input end of a servo driver with a corresponding address number through a data sending port.

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license. Disclosed example licensor systems further include a configuration installation code generator to generate feature configuration installation code, the feature configuration installation code to be used by the third party to generate at least a portion of the license, the portion of the license to be used by a licensee to configure the silicon structure to access the licensed feature, and contents of the feature configuration installation code encrypted to prevent access by the authorized delegated licensor.

A manufacturing process system includes: a plurality of processing devices which processes workpieces, with respective equipment associated with the plurality of processing devices; a transfer device which transfers the workpieces to the plurality of processing devices; a host computer which performs creating a transfer plan including information of timings at which the workpieces are carried in and out by the transfer device and acquiring an operation schedule including information of maintenance time from the plurality of processing devices; and a processing device group controller which performs acquiring the transfer plan and the operation schedule from the host computer, comparing the transfer plan and the operation schedule of each processing device, specifying the last process before maintenance for each processing device, detecting the end timing of the specified process, and instructing each processing device to be switched to an idle state at the end timing along with the associated equipment.

A production system includes a manufacturing apparatus, a post-processing apparatus, conveyors for transporting workpieces manufactured by the manufacturing apparatus to the post-processing apparatus, an image sensor arranged above a conveyor connected to the manufacturing apparatus to recognize workpieces traveling on the conveyor and measure the workpiece density on the conveyor, a robot that picks each workpiece on the conveyor connected to the manufacturing apparatus, and a controller. The controller performs a first task for identifying each workpiece position on the conveyor using a recognition result from the image sensor and causing the robot to pick a target workpiece, a second task for processing in the manufacturing apparatus, a third task for processing in the post-processing apparatus, and a fourth task for adjusting a processing capability of the manufacturing apparatus and/or the post-processing apparatus using the workpiece density measured by the image sensor.