Disclosed are a communication method between a master controller and slave controllers, a slave controller for the communication method, and a battery management system using the communication method and the slave controller, in which the master controller receives safety information about battery cells through a plurality of channels even when each of a plurality of slave controllers includes only one micro controller unit, thereby minimizing the increase in the cost and enhancing the safety of the battery management system. The communication method includes performing bidirectional communication between a master controller and first to N.sup.th (where N is an integer equal to or more than two) slave controllers through a first communication channel, and receiving, by the master controller, an indication signal through a second communication signal via the first to N.sup.th slave controllers.

According to certain embodiments, a system comprises a master device and a plurality of slave devices. The master device configured to determine that one or more of the slave devices use a default address reserved for unconfigured devices, and to communicate a command to each slave device that is using the default address. The command comprises a list of unused addresses and an instruction to enter a selection round to select one of the addresses from the list.

A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I.sup.2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.

A bus system is provided. The bus system includes a master device, a bus, and a plurality of slave devices electrically connected to the master device via the bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. When a first slave device communicates with the master device through the bus, in a first phase of a plurality of phases in each assignment period, the first slave device sets the alert-handshake control line to a first voltage level via the alert handshake pin, wherein the first phase corresponds to the first slave device. In the phases other than the first phase in each assignment period, the alert-handshake control line is at a second voltage level. Each of the phases includes two clock cycles.

A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

A main control section (30) of a slave device (3) include a slave controller (31), a processor (32), and a watchdog circuit (33) which are configured as a one-chip integrated circuit. In a case where the watchdog circuit (33) has detected that a malfunction has occurred in an operation of the main control section (30), the watchdog circuit (33) resets the processor (32) while not stopping an operation of the slave controller (31).

An electric power control system capable and a control device and a controlled device of electric power simplifying and reducing the cost of a slave device and electric power are provided. A power control system includes a master device supplied with power from a battery and a slave device powered by the battery through the master device. The slave device can also be supplied from a sub-battery or a solar cell that is different from the battery, the master device is provided with a control unit for controlling the slave device to be powered from the battery and the solar cell based on the power supply state of the battery and the solar cell.

A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Communication system and data rewriting method which can reduce the cost of an ECU are provided. A communication system includes a master ECU and a slave ECU configured to receive a communication frame from the master ECU, wherein the slave ECU includes a region for an operating program that controls a load connected to this slave ECU, and a region for a set value. The slave ECU is configured to rewrite the set value based on a communication frame transmitted from the master ECU.

A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I.sup.2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.