A substrate processing apparatus includes an operating unit for transmitting apparatus data to a memory, the apparatus data being required while a recipe for processing a substrate is executed; and a data matching unit for comparing the apparatus data stored in the memory. When an error occurs in the substrate processing apparatus, the operating unit transmits data representing the error to the data matching unit. The data matching unit includes: a selection unit for selecting first apparatus data which was acquired when the recipe was executed without an occurrence of the error, and stored in the memory; an acquisition unit for acquiring first and second apparatus data from the memory, the first apparatus data being acquired when an error did not occur and the second apparatus data being acquired when an error occurred; and a calculation unit for comparing the first and second apparatus data and calculating a difference therebetween.

Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving information describing a defect. The method further includes identifying a critical area of a silicon wafer and determining the probability of the defect occurring in the critical area. The method further includes determining, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The method further includes providing, based on the likelihood, predictive information to a manufacturing system. In some embodiments, corrective action may be taken based on the predictive information in order to improve silicon wafer manufacturing.

There is provided a method and a system configured to obtain an image of a one or more first areas of a semiconductor specimen acquired by an examination tool, determine data D.sub.att informative of defectivity in the one or more first areas, determine one or more second areas of the semiconductor specimen for which presence of a defect is suspected based at least on an evolution of D.sub.att, or of data correlated to D.sub.att, in the one or more first areas, and select the one or more second areas for inspection by the examination tool.

Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.

According to one embodiment, a controller calculates an estimation temperature profile, which represents a change with time in temperature of a substrate mounting surface in a state where a substrate is placed on a substrate stage, from warp amount information indicating a warp of the substrate. Further, the controller detects abnormality of a placement state of the substrate, on a basis of a difference between an actual measurement temperature profile, which represents a change with time in actual temperature measured by a temperature sensor in a state where the substrate is placed on the substrate stage, and the estimation temperature profile.

A substrate processing apparatus includes a process station for processing a substrate; a cassette station integrated with the process station; a substrate carriage equipped for transferring the substrate between said process station and the cassette station through a passage located at an interface between the process station and said cassette station; and a substrate scanner equipped at said interface between the process station and the cassette station for capturing surface image data during transportation of the substrate that passes through the passage.

In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.

An advanced process control system including a first process tool, a second process tool, and a measurement tool is provided. The first processing tool is configured to process each of a plurality of wafers by one of a plurality of first masks, and provide a first process timing data. The second processing tool is configured to process the wafer processing by the first process tool by one of a plurality of second masks to provide a plurality of works. The second process tool provides a measurement trigger signal according to the first process timing data. The measuring tool is configured to determine whether to perform a measuring operation on each works in response to the measurement trigger signal, and correspondingly provide a measurement result.

Methods and metrology modules are provided, which derive landscape information (expressing relation(s) between metrology metric(s) and measurement parameters) from produced wafers, identifying therein indications for production process changes, and modify production process parameters with respect to the identified indications, to maintain the production process within specified requirements. Process changes may be detected in wafer(s), wafer lot(s) and batches, and the information may be used to detect root causes for the changes with respect to production tools and steps and to indicate tool aging and required maintenance. The information and its analysis may further be used to optimize the working point parameters, to optimizing designs of devices and/or targets and/or to train corresponding algorithms to perform the identifying, e.g., using training wafers.

According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.