Patent classifications
G05B2219/45027
Method for grouping region of interest of mask pattern and measuring critical dimension of mask pattern using the same
A method for measuring a critical dimension of a mask pattern, including generating a mask pattern using an optically proximity-corrected (OPC) mask design including at least one block; measuring a first critical dimension of a target-region of interest (target-ROI) including neighboring blocks having a same critical dimension (CD), in the mask pattern; determining a group region of interest including the target-ROI and at least one neighboring block adjacent to the target-ROI; measuring second CDs of the neighboring blocks of the group region of interest; and correcting a measuring value of the first CD using a measuring value of the second CDs.
Semiconductor wafer cooling
A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.
SEMICONDUCTOR WAFER COOLING
A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.