In a method for controlling the positioning of patterns on a substrate in a manufacturing process at least one registration measurement is conducted with a registration tool on at least one pattern formed in at least one layer on the substrate by a previous process step of the manufacturing process. From the registration measurement a position of the at least one pattern in a coordinate system is determined. The determined position of the at least one pattern is fed into an automatic process control of a manufacturing system for controlling a setup of the manufacturing system for a subsequent process step of the manufacturing process. The manufacturing process may be a wafer manufacturing process with a silicon substrate. Complementary information may be collected in addition to performing the registration measurement and fed to the automatic process control. The process steps may for example include lithography steps, etching steps, layer deposition.

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.

An inspection system includes a controller communicatively coupled to a physical inspection device (PID), a virtual inspection device (VID) configured to analyze stored PID data, and a defect verification device (DVD). The controller may receive a pattern layout of a sample including multiple patterns fabricated with selected lithography configurations defining a process window, receive locations of PID-identified defects identified through analysis of the sample with the PID, wherein the PID-identified defects are verified by the DVD, remove one or more lithography configurations associated with the locations of the PID-identified defects from the process window, iteratively refine the process window by removing one or more lithography configurations associated with VID-identified defects identified through analysis of selected portions of stored PID data with the VID, and provide, as an output, the process window when a selected end condition is met.

There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

A method including: determining a value of a characteristic of a patterning process or a product thereof, at a current value of a processing parameter; determining whether a termination criterion is met by the value of the characteristic; if the termination criterion is not met, determining a new value of the processing parameter from the current value of the processing parameter and a prior value of the processing parameter, and setting the current value to the new value and repeating the determining steps; and if the termination criterion is met, providing the current value of the processing parameter as an approximation of a value of the processing parameter at which the characteristic has a target value.

A device manufacturing method, the method comprising: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.

A method for configuring a semiconductor manufacturing process, the method including: obtaining a first value of a first parameter based on measurements associated with a first operation of a process step in the semiconductor manufacturing process and a first sampling scheme; using a recurrent neural network to determine a predicted value of the first parameter based on the first value; and using the predicted value of the first parameter in configuring a subsequent operation of the process step in the semiconductor manufacturing process.

A set of original model candidates are first grouped into pairs of original model candidates. A pair of child model candidates is generated for each of the pairs of original model candidates by performing mutation, crossover, or both on the each of the pairs of original model candidates. From the original model candidates and the child model candidates, a set of new model candidates are derived, which includes pairing, based on a similarity function, each child model candidate with one of the corresponding original model candidates; selecting one or both of the model candidates in each of the parent-child pairs based on the similarity function and an objective function as new model candidates; and performing niche clearing to keep a number of the new model candidates in each of niches from exceeding a maximum number. The grouping, generating and deriving operations are then iterated.

A method including obtaining a fit of data for overlay of a metrology target for a patterning process as a function of a stack difference parameter of the metrology target; and using, by a hardware computer, a slope of the fit (i) to differentiate a metrology target measurement recipe from another metrology target measurement recipe, or (ii) calculate a corrected value of overlay, or (iii) to indicate that an overlay measurement value obtained using the metrology target should be used, or not be used, to configure or modify an aspect of the patterning process, or (iv) any combination selected from (i)-(iii).