A system and method of shaping a film with a template on a substrate. Generating a first series of parameters from tests performed on a first series of films formed with: a set of shaping conditions; a calibration measurement parameter determined for each substrate prior to shaping; and a first scaling parameter. Generating a second series of parameters from the tests performed on a second series of films produced formed with the set of shaping conditions. The second series of films produced with the calibration measurement parameter determined for each substrate; and a second scaling parameter; or without the calibration measurement parameter. Generating a scaling parameter from: the first series of the parameters; and the second series of parameters. Generating the calibration measurement parameter prior to forming the film. Forming the film using the set of shaping conditions, the calibration measurement parameter, and the scaling parameter.

A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

A test artifact for additive manufacturing is provided. The artifact comprises an additively manufactured singular continuous body between 100 cc and 6 cc in bounding box volume and between 50 cc and 3 cc in solid body. The body comprises at least three fiducials positioned for identification of locations in cross-section after sectioning of the artifact and at least three geometries that are unique from each other when exposed in cross section.

A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

The feedback control device takes information regarding a control deviation between a measured value and a target value of a controlled object as input, and outputs a control amount for the controlled object; comprising: a first control unit that takes information regarding the control deviation as input, and outputs a first control amount for the controlled object; a second control unit that takes information regarding the control deviation as input and outputs a second control amount for the controlled object, and in which a parameter for calculating the second control amount is determined by machine learning; an operation unit that operates the controlled object using the first control amount output from the first control unit and the second control amount output from the second control unit; and a sampling unit for thinning out at a predetermined period information regarding the control deviation input to the second control unit.

A lithography device includes: a pattern forming unit that forms a pattern in a shot region on a substrate held by a substrate holding unit by using a pattern unit; an acquisition unit that acquires relationships among the amount of positional deviation of the substrate relative to the substrate holding unit, a holding force applied to at least a part of the substrate to hold the substrate, and an overlapping error between the substrate and the pattern unit; a measurement unit that measures the amount of positional deviation of the substrate relative to the substrate holding unit; and a control unit that controls the holding force to reduce the overlapping error between the substrate and the pattern unit on the basis of the amount of positional deviation measured by the measuring unit and the relationships acquired by the acquisition unit.

A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

A device manufacturing method, the method including: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.