A system for determining a processing procedure including a plurality of processes for controlling an object, the system includes a learning unit for performing a learning process for determining a processing condition of each of a plurality of processes, and the learning unit acquires a physical quantity correlating with a state of the object on which a process has been performed under a predetermined processing condition, from a device for controlling the object on the basis of the processing procedure, calculates a pseudo state corresponding to the state of the object on the basis of the physical quantity, performs a learning process using a value function, and determines a processing condition of each of the plurality of processes to achieve a target state of the object.

A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers. The system may also include a model selection engine configured to set a given candidate lithography model in the candidate lithography model set as a calibrated lithography model for simulating a lithographic process.

Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.

A method includes identifying first parameters of a first processing chamber of a semiconductor fabrication facility. The first parameters include first input parameters and first output parameters. The method further includes identifying second parameters of a second processing chamber of the semiconductor fabrication facility. The second parameters include second input parameters and second output parameters. The method further includes generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters and composite output parameters. Semiconductor fabrication is based on the composite parameters.

A method of determining topographical variation across a substrate on which one or more patterns have been applied. The method includes obtaining measured topography data representing a topographical variation across a substrate on which one or more patterns have been applied by a lithographic process; and combining the measured topography data with knowledge relating to intra-die topology to obtain derived topography data having a resolution greater than the resolution of the measured topography data. Also disclosed is a corresponding level sensor apparatus and lithographic apparatus having such a level sensor apparatus, and a more general method of determining variation of a physical parameter from first measurement data of variation of the physical parameter across the substrate and intra-die measurement data of higher resolution than the first measurement data and combining these.

A method for configuring a semiconductor manufacturing process, the method including: obtaining a first value of a first parameter based on measurements associated with a first operation of a process step in the semiconductor manufacturing process and a first sampling scheme; using a recurrent neural network to determine a predicted value of the first parameter based on the first value; and using the predicted value of the first parameter in configuring a subsequent operation of the process step in the semiconductor manufacturing process.

The invention relates to a device for examining and/or processing an element for photolithography with a beam of charged particles, wherein the device comprises: (a) means for acquiring measurement data while the element for photolithography is exposed to the beam of charged particles; and (b) means for predetermining a drift of the beam of charged particles relative to the element for photolithography with a trained machine learning model and/or a predictive filter, wherein the trained machine learning model and/or the predictive filter use(s) at least the measurement data as input data.

A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. A backscatter is calculated for the area of the pattern based on the exposure information. An artificial background dose is determined for the area. The artificial background dose comprises additional exposure information and is combined with the original set of exposure information creating a modified set of exposure information. A system for exposing a pattern in an area on a surface using a charged particle beam lithography is also disclosed.

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.