An annealing apparatus includes a heater plate and a cooler plate disposed in a chamber, a delivering robot, a sensor and circuitry. The delivering robot is configured to deliver a wafer between the heater plate and the cooler plate in the chamber. The sensor is located on the delivering robot and configured to output a first signal in response to a motion of the delivering robot. The circuitry is coupled to the sensor and configured to detect whether an abnormality of the delivering robot occurs according to the first signal.

Methods and systems for reducing substrate particle scratching using machine learning are provided. A machine learning model is trained to predict process recipe settings for a substrate temperature control process to be performed for a current substrate at a manufacturing system. First training data and second training data are generated for the machine learning model. The first training data includes historical data associated with prior process recipe settings for a prior substrate temperature control process performed for a prior substrate at a prior process chamber. The second training data is associated with a historical scratch profile of one or more surfaces of the prior substrate after performance of the prior substrate temperature control process according to the prior process recipe settings. The first training data and the second training data are provided to train the machine learning model to predict which process recipe settings for the substrate temperature control process to be performed for the current substrate correspond to a target scratch profile for one or more surfaces of the current substrate.

A system and method include receiving, by a processing device of a manufacturing execution system (MES), a target profile associated with products, wherein the target profile comprises an identifier of a block of steps in a process to make the products and a target work-in-progress (WIP) value representing a target number of parts waiting to be processed by a group of machines used in the block of steps to make the products, identifying a move list or an assignment list that, when issued, causes the group of machines to operate to maintain a number of parts waiting for processing to match the target WIP value of the target profile.

The subject matter of this specification can be implemented in, among other things, a method, system, and/or device to receive current metrology data for an operation on a current sample in a fabrication process. The metrology data includes a current value for a parameter at each of one or more locations on the current sample. The method further includes determining a current rate of change of the parameter value for each of the one or more locations. The current rate of change is associated with the current sample. The method further includes identifying one or more violating locations each having an associated current rate of change of the parameter value that is greater than an associated reference rate of change of the parameter value, and identifying an instance of abnormality of the fabrication process based on the one or more violating locations.

Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

Disclosed techniques for applying a neural network deep learning model in a fabrication strategy for high-mix semiconductor manufacturing, such as deposition, chemical-mechanical polishing (CMP), etching, photolithography, plating, etc. Training and normal operation modes of the fabrication strategy are described.

Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

A substrate processing system comprises a module to perform an operation associated with processing a semiconductor substrate in the substrate processing system. The module includes a component used with the processing of the semiconductor substrate, and a file stored in the module. The file includes information about the component of the module. The substrate processing system comprises a controller to communicate with the module via a network of the substrate processing system. The controller receives the file from the module via the network, reads the information about the component from the received file, and maps, based on the information read from the received file, the component of the module to an option in an application used to configure the module. The controller automatically configures the component of the module using the option in the application to which the component of the module is mapped.

A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.