Patent classifications
G05B2219/45032
SUBSTRATE TRANSFER APPARATUS, SUBSTRATE TRANSFER METHOD, AND NON-TRANSITORY STORAGE MEDIUM
A substrate transfer apparatus to transfer a circular substrate provided with a cutout at an edge portion thereof, includes: a sensor part including three light source parts applying light to positions different from one another at the edge portion, and three light receiving parts paired with the light source parts; and a drive part for moving the substrate holding part, wherein the three light source parts apply light to the light receiving parts so that whether or not a detection range of the sensor part overlaps with the cutout of the substrate is determined on the basis of an amount of received light by each light receiving part, and when it is determined that there is an overlap at any position, positions of the edge portion of the substrate are further detected with the position of the substrate displaced with respect to the sensor part.
Complementary metal-oxide silicon having silicon and silicon germanium channels
A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.
MATCHING PROCESS CONTROLLERS FOR IMPROVED MATCHING OF PROCESS
A method includes: generating composite input parameters using first input parameters of a first processing chamber and second input parameters of a second processing chamber; generating third input parameters by adjusting the first input parameters such that the third input parameters more closely approximate the composite input parameters than the first input parameters; generating fourth input parameters by adjusting the second input parameters such that the fourth input parameters more closely approximate the composite input parameters than the second input parameters; causing fabrication of first semiconductors in the first processing chamber in a third process run based on the third input parameters and corresponding to a lower yield loss than the first process run; and causing fabrication of second semiconductors in the second processing chamber in a fourth process run based on the fourth input parameters and corresponding to a lower yield loss than the second process run.