Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

An over temperature compensation control circuit is coupled to a conversion unit. The over temperature compensation control circuit includes a detection circuit, a temperature control resistor, and a comparison unit. The detection circuit provides a current signal responsive to an input voltage according to a voltage signal responsive to the input voltage of the conversion unit. The temperature control resistor generates a temperature control voltage according to the current signal. The comparison unit compares the temperature control voltage with a reference voltage to generate a control signal. The control signal represents whether a temperature of the conversion unit reaches an over temperature protection point.

A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.

An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.

A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

Resonant converters may be operated according to selected working modes to achieve voltage doubler or non-voltage doubler functions. Embodiments may be based on two-phase resonant converters. Embodiments may implement primary side switching, secondary side switching, or both, to achieve the selected working modes and voltage doubler and non-voltage doubler function. Embodiments are suitable for applications requiring wide input and output voltage ranges, such as low-voltage charging circuits for personal electronic devices, and high voltage charging circuits for electric vehicles.

Vehicles and vehicle power circuits are disclosed for providing multiple different voltages from the same power source. An example vehicle includes a power source, a plurality of electrical loads, and a power circuit. The power circuit is electrically connected to the power source and the plurality of electrical loads. The power circuit includes a plurality of power segments connected in parallel to the power source, each power segment comprising a DC to DC converter and an ultra capacitor in series with the DC to DC converter, wherein the ultra capacitors of the plurality of power segments are connected in series.

A system, method and computer program product for operating a low-voltage Internet-of-Things sensor device. The method includes sensing of the temperature dependence at each voltage condition in addition to the actual temperature and voltage. A programmed machine learning model uses the information to decide when it is appropriate to test the device functionality and use the results of different tests to determine when the system should run synchronously or asynchronously through a machine learning predictive algorithm. Based on said one or more sensed operating conditions, the system uses the model to detect a mode of operation of said IoT device indicating IoT device meets an expected level of performance, or a mode indicating said IoT device is not operating according to the expected level of performance. Based on the detected operating condition, the IoT device automatically adapts its operation to ensure a desired level of IoT sensor device performance.