A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.

Techniques for controlling a low-dropout (LDO) voltage regulator. In an example, an LDO voltage regulator circuit includes an amplifier having an output coupled to a transistor. First and second inputs of the amplifier are coupled to a power supply node via first and second resistors, respectively. The transistor gate is coupled to the amplifier output, the transistor source is coupled to the second input of the amplifier, and the transistor drain is coupled to a reference voltage node. The second resistor is variable based on the amplifier output and a reference voltage from the reference voltage node. In an example, the reference voltage node is connectable to ground via a reference resistor connected in parallel with a noise-filtering capacitor, which causes a reference current to flow through the transistor. The reference current is adjusted based on the drain-to-source voltage of the transistor.

A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.

Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

A voltage regulator is provided. The voltage regulator includes a main error amplifier, a first buffer, a second buffer, and multiple main zero compensation loops. The main error amplifier generates a first voltage signal according to a reference voltage signal and a feedback voltage signal. The first buffer provides a second voltage signal according to the first voltage signal. The second buffer provides an output voltage signal according to the second voltage signal. The main zero compensation loops are respectively coupled between an output terminal of the main error amplifier and an output terminal of the first buffer. The main zero compensation loops provide different zero compensations.

A voltage regulator circuit can include two feedback loops, such as to reduce or suppress an unwanted transient condition in an output voltage during transient conditions such as during startup or during load current demand transients. One of the two feedback loops can include a shunt device arranged to provide a temporary current pathway during the transient condition to change current provided to a load connected to an output of the voltage regulation circuit. In addition, or instead, the voltage regulator circuit can include an open-loop regulation circuit separate from a loop corresponding to the first error amplifier. The open-loop regulator circuit can operate in a lower-power mode as compared to a closed-loop regulator circuit. A portion or an entirety of the voltage regulator circuit can be implemented in an integrated circuit, such as monolithically.

There is provided a digital voltage regulator, which includes a first comparator, a circuit switching circuit, a voltage regulation control circuit, a first transistor array and a second transistor array; a width-to-length ratio of any one of transistors in the first transistor array is larger than that of any one of transistors in the second transistor array; the first comparator outputs a comparison result between a first reference voltage and an output voltage; the voltage regulation control circuit generates a voltage regulating signal according to the comparison result under control of a clock signal; the circuit switching circuit controls one of the first transistor array and the second transistor array according to a comparison result between the output voltage and a second reference voltage and a comparison result between the output voltage and a third reference voltage to regulate the output voltage based on the voltage regulating signal.

An on-chip resistor correction circuit includes a first MOS transistor connected between VDD and a reference resistor, the other end of the reference resistor being grounded; an operational amplifier for outputting a first control signal based on a reference voltage and a voltage of the reference resistor; a second MOS transistor connected between VDD and a reference node; a branch where each of the on-chip resistors is located is controllably connected between the reference node and ground; a comparator for generating a comparison signal based on the voltage of the reference node and the reference voltage; and a controller for generating a control signal under the action of the comparison signal to control the branch where each of the on-chip resistors is located to turn on or off.

A circuit includes a reference voltage generator circuit and a regulation loop circuit having an output voltage terminal. The regulator circuit further includes a fault detection circuit having a first input terminal coupled to the output voltage regulator terminal of the regulation loop circuit. The fault detection circuit asserts, on an output terminal of the fault detection circuit, a fault flag signal responsive to a voltage on the first input terminal falling below a first threshold. A programmable filter is coupled between the reference voltage generator circuit and the regulation loop circuit and is coupled to the fault detection circuit. The programmable filter has a programmable time constant. The programmable filter responds to an assertion of the fault flag signal by decreasing the time constant.

The present disclosure relates to an amplifying circuit and a voltage generating circuit. The amplifying circuit includes: an operational amplifier, including a first input terminal, a second input terminal and an output terminal, and configured to be capable of outputting an output voltage corresponding to an input voltage from the output terminal to the first input terminal; a voltage dividing circuit, including a series circuit of a plurality of voltage dividing resistors disposed between the output terminal and a predetermined potential terminal, wherein the series circuit includes a feedback node connected to the second input terminal and a correction node different from the feedback node; and a correction circuit, including a diode inserted between the correction node and the predetermined potential terminal.