This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.

This disclosure relates to power balancer circuits that enable multiple load zones of an IC to be powered in series while maintaining balanced voltage at each load zone. In one aspect, a circuit includes load zones that are powered in series. The circuit includes a power balancer for balancing a voltage across each load zone. The power balancer includes an equivalent DC transformer array that includes, for each load zone, an equivalent DC transformer connected in parallel with the load zone. The power balancer includes, for each load zone, a bus capacitor connected in parallel with the load zone. Each equivalent DC transformer is electrically connected to each other equivalent DC transformer providing an electrical path for each bus capacitor to discharge current to each other bus capacitor when a voltage across a bus capacitor is greater than a voltage across another bus capacitor.

A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

A power supply and a method to provide power to a load via a power delivery network are presented. The power delivery network adds a pole and/or zero to a transfer function of the power supply. The power supply has a feedback unit to sense a load voltage at the load and to provide a feedback voltage which is indicative of the load voltage. The power supply has an input amplifier provides an error voltage based on the feedback voltage. The power supply has a power converter to provide power to the power delivery network depending on the error voltage. The power supply has an equalization unit to add a zero and/or a pole to the transfer function of the power supply, such that the pole and/or zero of the power delivery network is partially compensated. The equalization unit is located between an input amplifier and a power converter.

A power supply circuitry includes a first transistor, a feedback circuit, a first differential amplifier circuit, a second differential amplifier circuit, and a first control circuit. The first transistor outputs a power supply voltage based on a drive signal. The feedback circuit generates a feedback voltage of the power supply voltage. The first differential amplifier circuit amplifies a difference between the feedback voltage and a reference voltage, and outputs the drive signal. The second differential amplifier circuit amplifies a difference between the reference voltage and the feedback voltage. The first control circuit detects a change in the power supply voltage by using a differentiation circuit and controls the power supply voltage based on an output of the second differential amplifier circuit.

Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

A low-dropout regulator (LDO) capable of providing high power-supply rejection ratio (PSRR) and good reverse isolation. The LDO may include a core circuitry and a reverse isolation circuitry. The core circuitry may include a PSRR circuitry coupled to an output node and configured to provide high PSRR at the output node. The reverse isolation circuitry may be configured to provide good reverse isolation at the output node by, for example, providing current in response to ripples at the output node. The reverse isolation circuitry may be configured with bandwidth higher than that of the core circuitry such that it can provide fast transient response. The reverse isolation circuitry may be configurable and/or reconfigurable for a desirable reverse isolation performance. The reverse isolation circuitry may be configurable and/or reconfigurable to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

A constant voltage circuit includes a depletion transistor having a drain, a gate, and a source, the drain connected to a first power supply terminal, and the gate connected to the source, a voltage division circuit connected between the first power supply terminal and an output terminal, a first enhancement transistor having a drain connected to the source of the depletion transistor, a source connected to the output terminal, and a gate connected to an output terminal of the voltage division circuit, a second enhancement transistor having a source connected to the first power supply terminal, a drain connected to the output terminal, and a gate connected to the drain of the first enhancement transistor, and a pull-down element having one end connected to the output terminal and the other end connected to a second power supply terminal.

Techniques for efficient operation of a linear stage in an H-bridge system are provided. In an example, a linear stage can switch between voltage regulation and current regulation over a range of a command signal. The particular regulation mode can depend on the regulation mode of a switched stage of the H-bridge system. Efficiency can he realized by using current regulation of the linear stage when the output voltage of the linear stage moves away from the voltage of a supply rail. Such a control scheme can reduce the voltage across the linear stage for a larger range of the command signal resulting in less heat dissipation of the linear stage compared to conventional control of H-bridge linear stages.