A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

The present invention provides a touch panel and a controlling method thereof. The controlling method comprises: during a display period of the touch panel, turning on a bias voltage generation circuit to generate a bias voltage signal, turning on a reverse bias voltage generation circuit to generate a reverse bias voltage signal, turning on a positive voltage generation circuit to generate a positive voltage signal, turning on a negative voltage generation circuit to generate a negative voltage signal, and turning off a modulating voltage generation circuit; during a touch period of the touch panel, turning off the bias voltage generation circuit, the reverse bias voltage generation circuit, the positive voltage generation circuit, and the negative voltage generation circuit, and turning on the modulating voltage generation circuit to generate a modulating voltage signal, wherein the modulating voltage signal is same as a touch sensing signal of the touch panel.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

A voltage detector comprising, a first voltage reference generator for generating a first voltage reference signal; a second voltage reference generator for generating a second voltage reference signal, wherein the second voltage reference signal is higher than the first voltage reference signal; a trigger, powered by an input signal to the voltage detector, and having an input for receiving either the first or second voltage reference signal and an output for generating a detection signal; and a switch for selectively connecting the input of the trigger to the first or second voltage reference signal, wherein the switch is operative to connect the input of the trigger to the first voltage reference signal when the detection signal output by the voltage detector is low and is operative to connect the input of the trigger to the second voltage reference signal when the detection signal output by the voltage detector is high, and a voltage detector system for monitoring an input signal and outputting a detection signal when a voltage of the input signal meets a first threshold, the voltage detector system comprising: a first voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the first voltage detector is configured to output the detection signal when the voltage of the input signal meets a first rising input voltage threshold, a second voltage detector having an input for receiving the input signal and an output for outputting a detection signal, wherein the second voltage detector is configured to output the detection signal when the voltage of the input signal meets a second rising input voltage threshold which is higher than the first threshold, wherein the output of the second voltage detector controls a connection between the input signal and the input of the first voltage detector such that when the voltage of the input signal meets the second rising input voltage threshold the connection between the input and the input of the first voltage detector is inhibited or disconnected.