Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

A sequence signal generator and a sequence signal generation method are provided. In the sequence signal generation method, a waveform output instruction sent by a host computer is received to acquire waveform data. The waveform data includes original square wave sequence data and target square wave sequence data, and the target square wave sequence data includes a preliminary delay parameter and a secondary delay parameter. An original square wave sequence signal is acquired according to the original square wave sequence data. According to the preliminary delay parameter, preliminary delay processing is performed on the original square wave sequence signal to acquire an intermediate square wave sequence signal, and according to the secondary delay parameter, secondary delay processing is performed on the intermediate square wave sequence signal to acquire a target square wave sequence signal.

A trigonometric function calculating device includes: an address generator that generates an address signal that is formed from plural bit strings and corresponds to a phase; a trigonometric function table that stores first sines and first cosines that respectively correspond to phases expressed by upper bits of the address signals, and second sines and a second cosines that respectively correspond to phases expressed by lower bits of the address signals; a calculation circuit that outputs, as a calculated value, a sine that corresponds to the address signal by calculating processing using the first sine, the first cosine, the second sine and the second cosine that correspond to the address signal and have been extracted by referring to the trigonometric function table; and a correcting section that corrects the calculated value on the basis of a correction value corresponding to the address signal.

Computationally efficient mixed precision floating point waveform generation takes advantage of the high-speed generation of waveforms with single-precision floating point numbers while reducing the generally unacceptable loss of precision of pure single-precision floating point to generate any waveform that repeats in 2. This approaches computes a reference phase in double precision as the modulus of the phase with 2 and then computes offsets to that value in single precision. The double precision reference phase is recomputed as needed depending on how quickly the phase grows and how large a machine epsilon is desired.

Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system further includes a control circuit comprising a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits and to selectively enable a provision of a voltage signal to a selected one of the charge locking circuit,

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Systems and components for use with neural networks. An execution block and a system architecture using that execution block are disclosed. The execution block uses a fully connected stack of layers and one output is a forecast for a time series while another output is a backcast that can be used to determine a residual from the input to the execution block. The execution block uses a waveform generator sub-unit whose parameters can be judiciously selected to thereby constrain the possible set of waveforms generated. By doing so, the execution block specializes its function. The system using the execution block has been shown to be better than the state of the art in providing solutions to the time series problem.

An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.

An apparatus includes a digital frequency synthesizer (DFS). The DFS includes a time-to-digital converter (TDC) to provide an output signal that represents a phase difference between a reference signal and a feedback signal. The DFS further includes a scaling circuit, which has an adaptively changed gain, to provide a scaled residue signal used to cancel an effect of the residue signal in the DFS.