Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.

Systems and methods for direct digital synthesis are disclosed. A direct digital synthesis system includes a direct digital synthesizer (DDS) and a programmable logic device (PLD) configured to control the DDS. The DDS includes at least one digital analog converter (DAC) and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS DAC and an NMOS DAC and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS transistor structures, which may be variable, and a pair of variable current sources. The PLD is configured to control variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

There are provided a waveform memory that stores waveform data of an arbitrary waveform, a control unit that outputs the waveform data stored in the waveform memory in time-series order at predetermined time intervals, a waveform signal generation unit that generates a waveform signal by D/A converting the output waveform data, and a data processing unit that sequentially calculates waveform data in time-series order based on pulse pattern data, in which the control unit outputs the sequentially calculated waveform data from the data processing unit to the waveform signal generation unit at predetermined time intervals, and causes the waveform signal generation unit to generate a waveform signal by D/A conversion. The control unit includes a data working unit that executes data working processing on designated pulse pattern data, and generates worked waveform data having a capacity, which is storable in the waveform memory, at a data preparation stage.

A signal generator for producing periodic signals for a measuring apparatus of automation technology. The signals have sequential, discrete signal frequencies, which lie within a predetermined frequency range. A control- and/or computing unit, a clock signal producer are provided, wherein the clock signal producer provides a constant sampling frequency, which is greater than the maximum discrete signal frequency in the predetermined frequency range. A memory unit is provided, in which for each of the discrete signal frequencies the amplitude values of the corresponding periodic signals are stored or storable as a function of the sampling frequency. The control- and/or computing unit reads out the stored or storable amplitude values of the discrete frequencies successively with the sampling frequency of the clock from the memory unit and produces the periodic signals, or forwards for producing. A static filter unit, is also provided with a limit frequency, which lies above the maximum signal frequency and which removes frequency fractions caused by the sampling.

A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2.sup.D1-1 phase boundary value records corresponding to 02.sup.D1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave according to the final interpolation data information of the sine wave.

An apparatus for generating a sinusoid at a pre-set frequency f includes a DC power source with a controllable output voltage, a transformer, a power switch, a sequencer, and an output filter. The power switch is configured to apply the output of the DC power source to the primary of the transformer in either direction or to remain off based on control signals that are applied to its control input. The sequencer applies control signals to the control input in a choreographed sequence to form an oversampled version of a sine wave. The output filter is connected to the secondary of the transformer, and it passes the pre-set frequency f and attenuates frequencies above a cut-off frequency. In some preferred embodiments, the cut-off frequency is 3f and the transfer function of the output filter has a zero at 5f.

An FM-CW radar includes a high frequency circuit that receives a reflected wave from a target, and a signal processing unit that converts an analog signal generated by the high frequency circuit into a digital signal and detects at least a distance to the target and velocity of the target. The high frequency circuit includes a VCO that receives a modulation voltage from the signal processing unit and generates a frequency-modulated high frequency signal. The signal processing unit includes an LUT that stores default modulation control data. The signal processing unit calculates frequency information from phase information of output of the VCO, and updates the data stored in the LUT with correction data that is generated by using a result of the calculation.