A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

A circuit device includes a first terminal, a second terminal, a receiving circuit configured to receive the differential signals via the first terminal and the second terminal, a first signal line connecting a first input terminal of the receiving circuit and the first terminal, a second signal line connecting a second input terminal of the receiving circuit and the second terminal, a first capacitor circuit having one end connected to the first signal line, a second capacitor circuit having one end connected to the second signal line, and a detection circuit configured to detect a duty cycle of an output signal that is output from the receiving circuit.

Disclosed is a semiconductor device and a clock system including a pulse laser-based clock distribution network. The semiconductor device includes a current pulse generator that generates a current pulse train based on a first optical pulse train and a second optical pulse train, a clock distribution network that outputs a clock based on the current pulse train, a CDN detector that detects at least one of status information of the clock distribution network and the output clock to generate detection information, and control logic that generates a control signal for regulating a current of the current pulse train based on the detection information.

A storage system includes a protective housing member configured to mate with a handheld electronic device. The protective housing member includes a charging area formed between a surface of the protective housing member and a surface of an accessory item of the handheld electronic device. The charging area is configured to charge the accessory item of the handheld electronic device. The charging area is powered by at last one power component of the protective housing member or at least one power component of the handheld electronic device. The storage system further includes at least one integrated circuit which is either a component of the handheld electronic device or a component of the protective housing member.

A low-jitter digital clock signal generating system which uses optical pulses output from a pulse laser includes a first balanced photodetector that converts first and second optical pulses with a delayed time interval into first and second electrical pulses through first and second photodiodes and outputs first and second modulated pulses generated by allowing the first and second electrical pulses to partially overlap each other, a second balanced photodetector that converts third and fourth optical pulses with the delayed time interval into third and fourth electrical pulses through third and fourth photodiodes, and outputs a second modulated pulse generated by allowing the third and fourth electrical pulses to partially overlap each other, and a capacitor. The capacitor is charged by the first modulated pulse, is discharged by the second modulated pulse, and outputs a voltage according to the charging and discharging as a clock signal.

An information processing apparatus includes a first transceiver configured to establish synchronous communication with each of a first apparatus and a second apparatus under a first wireless communication standard, and a second transceiver configured to communicate with a third apparatus under a second wireless communication standard, and a control circuit. The control circuit is configured to perform timing adjustment processing for adjusting, for providing a period of communication by the second transceiver, at least any one of timing of synchronous communication with the first apparatus and timing of synchronous communication with the second apparatus such that a time point of end of synchronous communication with the first apparatus by the first transceiver is substantially continuous to a time point of start of synchronous communication with the second apparatus by the first transceiver.

A system for generating clock signals for a photonic quantum computing system includes a pump photon source configured to generate a plurality of pump photon pulses at a first repetition rate, a waveguide optically coupled to the pump photon source, and a photon-pair source optically coupled to the first waveguide. The system also includes a photodetector optically coupled to the photon-pair source and configured to generate a plurality of electrical pulses in response to detection of at least a portion of the plurality of pump photon pulses at the first repetition rate and a clock generator coupled to the photodetector and configured to convert the plurality of electrical pulses into a plurality of clock signals at the first repetition rate.

A storage system includes a protective housing member configured to mate with a handheld electronic device. The protective housing member includes a charging area formed between a surface of the protective housing member and a surface of an accessory item of the handheld electronic device. The charging area is configured to charge the accessory item of the handheld electronic device. The charging area is powered by at last one power component of the protective housing member or at least one power component of the handheld electronic device. The storage system further includes at least one integrated circuit which is either a component of the handheld electronic device or a component of the protective housing member.

In an aspect, an apparatus for distribution of frequency reference to a receiving end over a transmission medium comprises a first mixer adapted to mix a frequency reference signal having a reference frequency with a local oscillator signal having a local oscillator frequency to provide a forward frequency reference signal, a communication section adapted to transmit the forward frequency reference signal and receive a first backward frequency reference signal, a second mixer adapted to mix the first backward frequency reference signal with the local oscillator signal to provide a second backward frequency reference signal and a phase comparator and control circuit adapted to adjust the local oscillator frequency based on a phase shift of the second backward frequency reference signal so as to compensate for a phase shift of the forward frequency reference signal.

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.