Patent classifications
G06F1/3203
APPARATUSES AND METHODS
An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to determine that a first composite link of a plurality of composite PCIe links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold. The processing circuitry is further configured to determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold and selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.
APPARATUSES AND METHODS
An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to determine that a first composite link of a plurality of composite PCIe links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold. The processing circuitry is further configured to determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold and selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.
SYSTEM AND METHODS FOR SERVER POWER MANAGEMENT
A system and methods are provided for improving power efficiency of a data center, including: acquiring training data including power caps, utilization rates, and a measure of Service Level Agreement (SLA) compliance of one or more computer servers of the data center; creating a model for determining power caps according to measured utilization rates of the one or more computer servers, wherein the determined power caps, when applied to the one or more computer servers, reduce power consumption and meet the measure of SLA compliance; and applying the model, according to subsequent data received during a second operating period, to determine a power cap to apply to the one or more computer servers, wherein the subsequent data includes a subsequent utilization rate of the one or more computer servers.
Facilitating power conservation for devices based on likelihood of power usage level
Power conservation for devices is facilitated based on likelihood of power usage level. An example method can comprise determining, by a first device comprising a processor, that a second device is within a defined proximity of a third device, wherein the third device is determined to be operating in a mode according to a first power consumption operation that satisfies a defined condition, and wherein the operating in the mode according to the first power consumption operation is based on the third device being located at a defined location. The method can also comprise facilitating, by the first device, modification of the mode of the third device based on a determination of a likelihood of usage of a second power consumption operation by the third device. In various embodiments, the third device is configured to operate according to the power save mode or the extended discontinuous reception mode.
SYSTEMS AND METHODS FOR AUTONOMOUS HARDWARE COMPUTE RESILIENCY
Methods and systems for providing hardware compute resiliency by using a compute fabric that includes sensors and re-programmable data processing components.
Power supply device, power supply system, power supply control method, and recording medium
A power supply system includes circuitry that controls transition of an operation mode of the information processing apparatus from a first mode to a second mode in response to reception of user operation for transitioning to the second mode, the second mode being a mode in which electric power supplied to the information processing apparatus is less than that of the first mode, determines whether to release the second mode based on a detection result of a sensor that detects presence of a human, to output a first determination result, determines whether a first condition relating to the user operation is satisfied, to output a second determination result, and determines, based on the second determination result indicating that the first condition is satisfied, whether to allow releasing of the second mode based on the first determination result indicating that no human is detected.
Digital power supply with wireless monitoring and control
Provided is an apparatus and method for a digital power supply that can provide independent power control for two or more electrical loads. Some disclosed embodiments provide continuous, variable power and other disclosed embodiments provide discrete power levels. Disclosed embodiments may reduce the magnitude of harmonic currents and/or flicker introduced into a power system. Embodiments include a microprocessor that delivers power to electric loads using phase-controlled AC current. In some embodiments, the microprocessor may calculate a power array corresponding to a requested power for each electric load. Logic is provided for populating the power array in a pattern that reduces the magnitude of harmonic currents and flicker. Portions of the disclosure include a band controller for delivering power to achieve and maintain a desired target temperature, and a wireless controller for controlling temperature from a remote device.
Digital power supply with wireless monitoring and control
Provided is an apparatus and method for a digital power supply that can provide independent power control for two or more electrical loads. Some disclosed embodiments provide continuous, variable power and other disclosed embodiments provide discrete power levels. Disclosed embodiments may reduce the magnitude of harmonic currents and/or flicker introduced into a power system. Embodiments include a microprocessor that delivers power to electric loads using phase-controlled AC current. In some embodiments, the microprocessor may calculate a power array corresponding to a requested power for each electric load. Logic is provided for populating the power array in a pattern that reduces the magnitude of harmonic currents and flicker. Portions of the disclosure include a band controller for delivering power to achieve and maintain a desired target temperature, and a wireless controller for controlling temperature from a remote device.
Signal processing coordination among digital voice assistant computing devices
Coordinating signal processing among computing devices in a voice-driven computing environment is provided. A first and second digital assistant can detect an input audio signal, perform a signal quality check, and provide indications that the first and second digital assistants are operational to process the input audio signal. A system can select the first digital assistant for further processing. The system can receive, from the first digital assistant, data packets including a command. The system can generate, for a network connected device selected from a plurality of network connected devices, an action data structure based on the data packets, and transmit the action data structure to the selected network connected device.
Configuration of base clock frequency of processor based on usage parameters
A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.