Systems, apparatuses, and methods related to dynamic precision bit string accumulation are described. Dynamic bit string accumulation can be performed using an edge computing device. In an example method, dynamic precision bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and determining that a result of the iteration of the recursive operation contains a quantity of bits in a particular bit sub-set of the result that is greater than a threshold quantity of bits associated with the particular bit sub-set. The method can further include writing a result of the iteration of the recursive operation to a first register and writing at least a portion of the bits associated with the particular bit sub-set of the result to a second register.

Ring buffer storage circuitry is disclosed which stores a ring buffer comprising multiple slots to hold a queued se-quence of data items. Data processing circuitry executes a plurality of processes to add one or more data items to be processed to the queued sequence and to remove one or more data items for process-ing from the queued sequence. Each process is arranged to perform an acquire process to acquire at least one slot in the ring buffer and to subsequently perform a release process to release the at least one slot. Ring buffer metadata storage circuitry stores metadata for the ring buffer comprising a first reference indicator and a second reference indicator. Corresponding methods and instructions are also disclosed.

Ring buffer storage circuitry is disclosed which stores a ring buffer comprising multiple slots to hold a queued se-quence of data items. Data processing circuitry executes a plurality of processes to add one or more data items to be processed to the queued sequence and to remove one or more data items for process-ing from the queued sequence. Each process is arranged to perform an acquire process to acquire at least one slot in the ring buffer and to subsequently perform a release process to release the at least one slot. Ring buffer metadata storage circuitry stores metadata for the ring buffer comprising a first reference indicator and a second reference indicator. Corresponding methods and instructions are also disclosed.

A universal serial bus (USB) device includes a first storage device, a controller, and a second storage device. The first storage device is configured to store input packets to be transmitted to a USB host. The controller is configured to receive the input packets of the first storage device, respectively compute hash values of the input packets, and respectively label first identifiers in the input packets according to the hash values to correspond to one of cores of a central processing unit at the USB host end. Among the input packets, the input packets with the same hash value are labeled with the same first identifier. The second storage device is configured to store the input packets that are labeled with the first identifier. The controller is further configured to allow the input packets stored in the second storage device to be transmitted to the USB host.

A universal serial bus (USB) device includes a first storage device, a controller, and a second storage device. The first storage device is configured to store input packets to be transmitted to a USB host. The controller is configured to receive the input packets of the first storage device, respectively compute hash values of the input packets, and respectively label first identifiers in the input packets according to the hash values to correspond to one of cores of a central processing unit at the USB host end. Among the input packets, the input packets with the same hash value are labeled with the same first identifier. The second storage device is configured to store the input packets that are labeled with the first identifier. The controller is further configured to allow the input packets stored in the second storage device to be transmitted to the USB host.

A port is provided that utilized various techniques to manage contention for the same by controlling data that is written to and read from the port in multi-core assembly within a usable computing system. When the port is a sampling port, the assembly may include at least two cores, a plurality of buffers in operative communication with the at least one sampling ports, a non-blocking contention management unit comprising a plurality of pointers that collectively operate to manage contention of shared ports in a multi-core computing system. When the port is queuing port, the assembly may include buffers in communication with the queuing port and the buffers are configured to hold multiple messages in the queuing port. The assembly may manage contention of shared queuing ports in a multi-core computing system.

A port is provided that utilized various techniques to manage contention for the same by controlling data that is written to and read from the port in multi-core assembly within a usable computing system. When the port is a sampling port, the assembly may include at least two cores, a plurality of buffers in operative communication with the at least one sampling ports, a non-blocking contention management unit comprising a plurality of pointers that collectively operate to manage contention of shared ports in a multi-core computing system. When the port is queuing port, the assembly may include buffers in communication with the queuing port and the buffers are configured to hold multiple messages in the queuing port. The assembly may manage contention of shared queuing ports in a multi-core computing system.

Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.

Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.

The described technology is directed towards sending metadata related to a video to a client device, such as events that describe a portion of that video, such as in a hidden stream. In one or more implementations, the enhanced metadata comprises nodes used to build part of a relationship graph. This allows interested clients to switch between the feature playback and interacting with the metadata. Further, searches through the enhanced metadata may be performed to find matching video portions, and summaries or highlights of one or more videos may be assembled by accessing information in the enhanced metadata.