An imaging apparatus including a frame buffer executes high-speed shooting consecutively in plural sessions. An imaging element includes a buffer, an image producing unit, a managing unit, and an output unit. The image producing unit produces an image in the case where an empty capacity of any of plural areas in the buffer exceeds a predetermined threshold value. The managing unit causes an area whose empty capacity exceeds the predetermined threshold value, of the plural areas to retain the image as a buffering image. The output unit extracts the buffering image from the buffer and outputting the buffering image, in order of the retention of the buffering image.

An imaging apparatus including a frame buffer executes high-speed shooting consecutively in plural sessions. An imaging element includes a buffer, an image producing unit, a managing unit, and an output unit. The image producing unit produces an image in the case where an empty capacity of any of plural areas in the buffer exceeds a predetermined threshold value. The managing unit causes an area whose empty capacity exceeds the predetermined threshold value, of the plural areas to retain the image as a buffering image. The output unit extracts the buffering image from the buffer and outputting the buffering image, in order of the retention of the buffering image.

According to various embodiments, apparatuses and methods to communicate buffer allocation information are presented. The disclosed apparatuses and methods may include transmitting a buffer message by a wireless USB device to a wireless USB host, which may indicate an available storage space in a buffer of the USB device to store data from the USB host. The buffer message may be transmitted independent of whether or not the USB device has received a request message (e.g., from the USB host) for information relating the available storage space in the buffer. Additionally, the buffer message may be transmitted independent of any data exchange mechanism between the USB host and the USB device. The USB device may receive a data packet from the USB host, and transmit a data packet acknowledgement message including data packet status information, and information regarding the available storage space in the buffer.

According to various embodiments, apparatuses and methods to communicate buffer allocation information are presented. The disclosed apparatuses and methods may include transmitting a buffer message by a wireless USB device to a wireless USB host, which may indicate an available storage space in a buffer of the USB device to store data from the USB host. The buffer message may be transmitted independent of whether or not the USB device has received a request message (e.g., from the USB host) for information relating the available storage space in the buffer. Additionally, the buffer message may be transmitted independent of any data exchange mechanism between the USB host and the USB device. The USB device may receive a data packet from the USB host, and transmit a data packet acknowledgement message including data packet status information, and information regarding the available storage space in the buffer.

Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.

Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.

A computer system includes a hardware buffer controller. Memory access requests to a buffer do not include an address within the buffer and threads accessing the buffer do not access or directly update any pointers to locations within the buffer. The memory access requests are addressed to the hardware buffer controller, which determines an address from its current state and issues a memory access command to that address. The hardware buffer controller updates its state in response to the memory access requests. The hardware buffer controller evaluates its state and outputs events to a thread scheduler in response to overflow or underflow conditions or near-overflow or near-underflow conditions. The thread scheduler may then block threads from issuing memory access requests to the hardware buffer controller. The buffer implemented may be a FIFO or other type of buffer.

A computer system includes a hardware buffer controller. Memory access requests to a buffer do not include an address within the buffer and threads accessing the buffer do not access or directly update any pointers to locations within the buffer. The memory access requests are addressed to the hardware buffer controller, which determines an address from its current state and issues a memory access command to that address. The hardware buffer controller updates its state in response to the memory access requests. The hardware buffer controller evaluates its state and outputs events to a thread scheduler in response to overflow or underflow conditions or near-overflow or near-underflow conditions. The thread scheduler may then block threads from issuing memory access requests to the hardware buffer controller. The buffer implemented may be a FIFO or other type of buffer.

A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.

A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.