Patent classifications
G06F7/405
Optimal metastability-containing sorting via parallel prefix computation
In order to provide smaller, faster and less error-prone circuits for sorting possibly metastable inputs, a novel sorting circuit is provided. According to the invention, the circuit is metastability-containing.
Method and device for assisting with the navigation of a fleet of vehicles using an invariant Kalman filter
A method for assisting the navigation of a fleet of vehicles including main vehicle and a secondary vehicle movable relative to the main vehicle includes receiving data acquired by one or more sensors, the received data including relative kinematic data between the main vehicle and the secondary vehicle, and estimating a navigation state of the fleet of vehicles by an invariant Kalman filter using the received data as observations. The navigation state includes first variables representative of a first rigid transformation linking a frame attached to the main vehicle to a reference frame, and second variables representative of a second rigid transformation linking the frame attached to the main vehicle to a frame attached to the secondary vehicle. The invariant Kalman filter uses as binary operation an operation including a term-by-term composition of the first rigid transformation and of the second rigid transformation.
DATA STORAGE ON IMPLANTABLE MAGNETIZABLE FABRIC
The disclosure is directed to a system, device and method for data storage on implantable magnetizable fabric. The system includes implantable magnetizable fabric coupled to a graft segment of a prosthesis for being delivered into a body of a subject. The system includes information written on the implantable magnetizable fabric. The system further includes a magnetic detection device capable of, after the prosthesis is delivered into the body of the subject, detecting the implantable magnetizable fabric and accessing at least a portion of the information.
Vehicle navigation assistance method and device using an invariant Kalman filter and a navigation status of a second vehicle
A method for assisting with the navigation of a fleet of vehicles including a main vehicle and a secondary vehicle that is mobile in relation to the main vehicle, the method including receiving relative movement data, acquired by one or more sensors, between the main vehicle and the secondary vehicle, estimating a navigation status of the fleet of vehicles by an invariant Kalman filter using the received data as observations, the navigation status including first variables representing a first rigid transformation linking a location mark associated with the main vehicle to a reference point, and second variables representing a second rigid transformation linking a location mark associated with the main vehicle to a location mark associated with the secondary vehicle, the invariant Kalman filter using, as an internal composition law, a law including a term-by term composition of the first rigid transformation and the second rigid transformation.
METHOD AND APPARATUS WITH MULTI-BIT ACCUMULATION
A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.
MULTI-BIT ACCUMULATOR AND IN-MEMORY COMPUTING PROCESSOR WITH SAME
A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees according to an enable signal provided to the tristate logic circuits, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the 1-bit Wallace trees by a shift operation based on a clock signal.
HARDWARE TO PERFORM SQUARING
Methods of calculating a square of an input number in hardware logic are described. An m-bit number is received and Booth encoding is performed on different groups of three consecutive bits selected from the input to generate an encoded value for each of the groups. For each group, the method comprises forming a truncated string from the input number, generating an updated version of the truncated number and selecting a bit string based on the encoded value, the selected bit string comprising zeros or a left-shifted version of the updated version of the truncated number sign extended to a bit-width of 2m bits. The method further comprises combining the selected bit strings and square and sign bits for each group into an addition array; and summing the bits in the addition array.
Electronic Wireless Binary Transmitter to a Electronic Receiver
The Binary Transmitter and Receiver is a circuit for Binary information to travel through Air without wires from the end out FIG. 4 without wires.
The transmitter circuit and Receiver is powered by FIG. 2 (volt, current, amp), FIG. 1 (capacitance), and resistance with its information of 0 or 1 in a series or parallel circuit or both.
It was tested in wood (a box). To be housed in plastic (a polymer), tin, copper, metal or Metal alloy. To function with keys from 0-9 key punch, A-Z and special character's key punch, and other inputs and outputs
That uses switches, nor-gates, and-gate, diodes, resistors and capacitors FIGS. 1A and 1B for a functional transmitter and a functional receiver.
Mini technology is required in models for mobile traveling with Lithium batteries or non-Lithium batteries for its power source.
OUTPUT BLOCK FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY
In one example, a system comprises: a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array comprising: a current-to-voltage converter to convert current received from a column of the vector-by-matrix multiplication array into a voltage, an analog-to-digital converter to convert the voltage into digital bits, and a configuration circuit to convert the digital bits into unsigned digital bits.