A double-balanced FET mixer may include: single-ended RF port that receives or delivers single-ended RF signal; RF balun that converts the received single-ended RF signal into differential RF signal or generates delivered single-ended RF signal from received differential RF signal; local oscillator input port receives local oscillator signal; direct IF port receives or delivers an IF signal; and at least two FETs process the local oscillator signal and generate or process the differential RF signal and IF signal. The mixer may have no IF balun separate and distinct from tRF balun; may receive an input signal at RF port and generates output signal at IF port. The mixer may receive input signal at IF port and generate an output signal at the RF port, the output signal in either case being plus or minus the local oscillator signal. The double-balanced FET mixer may operate with IF frequencies down to DC.

A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

A method of determining the center of loading of a rolling element includes providing a rolling element body and at least three load sensors. The sensors are each positioned within a bore of the rolling element body at a separate distance from a reference position. Load measurements are taken with each one of the sensors at various positions about the circumference of the bearing and the center of loading is calculated at each one of the positions to determine the variation in axial loading about the bearing circumference.

A method of determining the center of loading of a rolling element includes providing a rolling element body and at least three load sensors. The sensors are each positioned within a bore of the rolling element body at a separate distance from a reference position. Load measurements are taken with each one of the sensors at various positions about the circumference of the bearing and the center of loading is calculated at each one of the positions to determine the variation in axial loading about the bearing circumference.

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.

At least one application is received from a user. The at least one application is stored on a communication platform. A catalog is received. The catalog includes at least one service. Each service of the at least one service is associated with a platform. An indication of a selection, from the user, is received. The selection comprises a first service associated with a first platform, and a second service associated with a second platform. The first service stores the at least one application from the user. The second service runs the at least one application from the user. Responsive to receiving the indication, the at least one application is deployed to the indicated first platform. Additionally, responsive to receiving the indication, a service bridge from the communication platform to the second platform is deployed. The at least one application is run, on the first platform utilizing the service bridge.

A method for optimizing an area of a ternary FPRM circuit using population migration algorithm, the method including: 1) establishing an area estimation model of the ternary FPRM circuit; 2) establishing a corresponding relationship between the ternary FPRM circuit and population migration algorithm; 3) setting an attraction function for calculating the attraction of the population location in population migration algorithm; 4) setting relevant parameters of population migration algorithm; and 5) employing population migration algorithm to calculate and obtain the greatest attractive site and the greatest attraction.