A method executed by a computer system that transmits a multimedia content through a negative-base number. The method includes generating a binary sequence for the multimedia content, converting the binary sequence into a negative-base number, receiving the negative-base number, retrieving a negative base of the negative base number, calculating the binary sequence based on the negative-base number and the negative base, and obtaining the multimedia content based on the binary sequence.

A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.

A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.

A system includes a memory and a node. The memory stores first and second log string correlithm objects. The node aligns the first and second log string correlithm objects such that a sub-string correlithm object from the first log string correlithm object associated with the logarithmic value of ten aligns with a sub-string correlithm object from the second log string correlithm object representing the logarithmic value of one. The node receives a first real-world numerical value and identifies a first sub-string correlithm object from the first log string correlithm object that corresponds to the first real-world numerical value. The node determines which sub-string correlithm object from the second log string correlithm object aligns in n-dimensional space with the first sub-string correlithm object from the first log string correlithm object, and outputs the determined sub-string correlithm object.

A method of sorting an array of data elements, the method includes assigning values associated with a monotonic function to the data elements, and sorting the array of data elements by sorting the monotonic function values using a least significant digit (LSD) Radix sort.

A method of sorting an array of data elements, the method includes assigning values associated with a monotonic function to the data elements, and sorting the array of data elements by sorting the monotonic function values using a radix sort.

A method of sorting an array of data elements, the method includes assigning values associated with a monotonic function to the data elements, and sorting the array of data elements by sorting the monotonic function values using a radix sort.

A multivalued microprocessor including a multivalued processing module having a plurality of multivalued processing units constructed with multivalued logic gates. The microprocessor also includes a multivalued register file having a plurality of registers, wherein the registers are constructed with multivalued memory cells. The multivalued microprocessors utilizes two memory modules constructed with multivalued memory cells: one for storing solely instructions and one for storing solely data. A plurality of multivalued buses transmit multivalued data between the processing module, the register file, and the memory modules. A methodology for designing multivalued circuits that are constructed with multivalued logic gates and memory cells. The designs of multivalued memory cells, multivalued tristate buffers, and multivalued decoders using multivalued logic gates.

A multivalued microprocessor including a multivalued processing module having a plurality of multivalued processing units constructed with multivalued logic gates. The microprocessor also includes a multivalued register file having a plurality of registers, wherein the registers are constructed with multivalued memory cells. The multivalued microprocessors utilizes two memory modules constructed with multivalued memory cells: one for storing solely instructions and one for storing solely data. A plurality of multivalued buses transmit multivalued data between the processing module, the register file, and the memory modules. A methodology for designing multivalued circuits that are constructed with multivalued logic gates and memory cells. The designs of multivalued memory cells, multivalued tristate buffers, and multivalued decoders using multivalued logic gates.

In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.