G06F7/491

Data computing system

The present disclosure provides a data computing system. The data computing system comprises: a memory, a processor and an accelerator, wherein the memory is communicatively coupled to the processor and configured to store data to be computed and a computed result, the data being written by the processor; the processor is communicatively coupled to the accelerator and configured to control the accelerator; and the accelerator is communicatively coupled to the memory and configured to access the memory according to pre-configured control information, implement a computing process to produce the computed result and write the computed result back to the memory. The present disclosure also provides an accelerator and a method performed by an accelerator of a data computing system. The present disclosure can improve the execution efficiency of the processor and reduce the computing overhead of the processor.

Method, apparatus, and computer program stored in computer readable medium for conducting arithmetic operation efficiently in database management server
11960460 · 2024-04-16 · ·

Provided are a method, an apparatus, and a computer program stored in a computer readable medium for conducting an arithmetic operation efficiently in a database management server. In a computer-readable medium including a computer program including encoded commands, which is configured to cause one or more processors to perform operations when the computer program is executed by the one or more processors of a computer system, the operations include: an operation of receiving a structure body creation request for performing a predetermined arithmetic operation; an operation of creating a structure body in response to the structure body creation request; an operation of receiving an arithmetic operation processing request of requesting processing of the predetermined arithmetic operation with respect to a plurality of numerical values; an operation of creating structure body number data for each of the plurality of numerical values by applying each of the plurality of numerical values to the created structure body, the created structure body including one or more array elements and at least some numerical values being allocated to the one or more array elements to create the structure body number data; and an operation of performing the predetermined arithmetic operation based on the structure body number data for each of the plurality of numerical values.

Method, apparatus, and computer program stored in computer readable medium for conducting arithmetic operation efficiently in database management server
11960460 · 2024-04-16 · ·

Provided are a method, an apparatus, and a computer program stored in a computer readable medium for conducting an arithmetic operation efficiently in a database management server. In a computer-readable medium including a computer program including encoded commands, which is configured to cause one or more processors to perform operations when the computer program is executed by the one or more processors of a computer system, the operations include: an operation of receiving a structure body creation request for performing a predetermined arithmetic operation; an operation of creating a structure body in response to the structure body creation request; an operation of receiving an arithmetic operation processing request of requesting processing of the predetermined arithmetic operation with respect to a plurality of numerical values; an operation of creating structure body number data for each of the plurality of numerical values by applying each of the plurality of numerical values to the created structure body, the created structure body including one or more array elements and at least some numerical values being allocated to the one or more array elements to create the structure body number data; and an operation of performing the predetermined arithmetic operation based on the structure body number data for each of the plurality of numerical values.

Round for reround mode in a decimal floating point instruction

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Round for reround mode in a decimal floating point instruction

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

Decimal floating point instructions to perform directly on compressed decimal floating point data

Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.

Decimal floating point instructions to perform directly on compressed decimal floating point data

Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.

Floating point unit with support for variable length numbers

Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Floating point unit with support for variable length numbers

Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR

A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3 generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3 generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.