A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K−1) iterations for deriving a remainder of a division of the first number by a second number.

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

A technique for bit depth up-conversion including obtaining an input value for a computation in a first bit depth with a fewer number of bits as compared to a second bit depth, converting the input value from the first bit depth to the second bit depth as an unsigned data value, adjusting a pointer to the converted input value based on the first bit depth, performing the computation based on the adjusted pointer to obtain an adjusted output value, and performing a right shift operation on the adjusted output value based on the first bit depth to obtain an output value.

In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2.sup.N−1 single-level-cell (SLC) flash cells for each synapse (Y.sub.i) connected to a bit line forming a neuron. The method includes the step of providing an input vector (X.sub.i) for each synapse Y.sub.i wherein each input vector is translated into an equivalent electrical signal ES.sub.i (current I.sub.DACi, pulse T.sub.PULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 2.sup.0*ES.sub.i to (2.sup.N−1)*ES.sub.i. The method includes the step of providing a set of weight vectors or synapse (Y.sub.i), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Y.sub.i). The method includes the step of providing for 2.sup.N possible threshold voltage levels or resistance levels in the 2.sup.N−1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Y.sub.i into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Y.sub.i). The method includes the step of turning off all remaining 2.sup.N−1 flash cells of the respective synapse (Y.sub.i).

Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Y.sub.i) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.

The specification unit 3 specifies a description part of an arithmetic expression that represents loop processing from an input source program. The generation unit 4 generates arithmetic expressions that represent executing, when a remainder when dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number, and executing loop processing with the designated unroll stage number after the processing of one loop. The replacement unit 5 replaces the arithmetic expression of the description part specified by the specification unit 3 with the arithmetic expressions generated by the generation unit 4.

The specification unit 3 specifies a description part of an arithmetic expression that represents loop processing from an input source program. The generation unit 4 generates arithmetic expressions that represent executing, when a remainder when dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number, and executing loop processing with the designated unroll stage number after the processing of one loop. The replacement unit 5 replaces the arithmetic expression of the description part specified by the specification unit 3 with the arithmetic expressions generated by the generation unit 4.

A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.

The present disclosure relates to a multiplier, a method, an integrated circuit chip, and a computation apparatus for a floating-point computation. The computation apparatus may be included in a combined processing apparatus, which may also include a general interconnection interface and other processing apparatus. The computation apparatus interacts with other processing apparatus to jointly complete computation operations specified by the user. The combined processing apparatus may also include a storage apparatus, which is respectively connected to the computation apparatus and other processing apparatus and is used for storing data of the computation apparatus and other processing apparatus. Solutions of the present disclosure may be widely used in various floating-point data computations

A floating-point operation control method, applied to a chip comprising a multiply accumulator, includes receiving a first selection signal, and controlling an operation circuit in the multiply accumulator corresponding to a floating-point operation mode indicated by the first selection signal. The floating-point operation mode supports a multiply accumulate operation of a floating-point number of a first bit width k.sub.1. The method further includes dividing fractional parts of first and second operands into m first and second suboperands of a second bit width k.sub.2. The second bit width k.sub.2=k.sub.1/m. The method further includes performing a multiplication operation based on the m first and second suboperands to obtain a fractional product, and determining a floating-point number sum based on the fractional product and a third operand.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log.sub.2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.