A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (m.sub.i) and an exponent (e.sub.i). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (m.sub.i) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (y.sub.i) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (m.sub.i). The method includes identifying a maximum exponent (e.sub.max) among the exponents e.sub.i, aligning the magnitude bits of the numbers (y.sub.i) based on the maximum exponent (e.sub.max) and processing the set of ‘k’ numbers concurrently.

A microprocessor splits a fused multiply-accumulate operation of the form A*B+C into first and second multiply-accumulate sub-operations to be performed by a multiplier and an adder. The first sub-operation at least multiplies A and B, and conditionally also accumulates C to the partial products of A and B to generate an unrounded nonredundant sum. The unrounded nonredundant sum is stored in memory shared by the multiplier and adder for an indefinite time period, enabling the multiplier and adder to perform other operations unrelated to the multiply-accumulate operation. The second sub-operation conditionally accumulates C to the unrounded nonredundant sum if C is not already incorporated into the value, and then generates a final rounded result.

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

A transmission method for transmitting measurements is taken by a fluid meter during successive measurement periods, each subdivided into successive time intervals. The measurements comprise first measurements, each representative of a quantity of fluid distributed during a respective one of the time intervals. The transmission method includes, for each measurement period, the step of producing and then transmitting at least one measurement frame such that: when the number of first measurements that are equal to zero is strictly less than a predetermined number during said measurement period, then the measurement frame is a normal measurement frame; otherwise the measurement frame is a compact measurement frame that, when there is at least one first measurement that is not equal to zero, comprises both preliminary data comprising identification data for identifying active time intervals and also compact first measurement data comprising only said non-zero first measurements ordered in a predefined order.

A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

An integrated circuit is provided with a modular multiplication circuit. The modular multiplication circuit includes an input multiplier for computing the product of two input signals, truncated multipliers for computing another product based on a modulus value and the product, and a subtraction circuit for computing a difference between the two products. An error correction circuit uses the difference to look up an estimated quotient value and to subtract out an integer multiple of the modulus value from the difference in a single step, wherein the integer multiple is equal to the estimated quotient value. A final adjustment stage is used to remove any remaining residual estimation error.

Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation.

An arithmetic operation device causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network. The arithmetic operation device includes: a bit reduction unit that reduces a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight that is an element of the filter for each convolution layer; and a bit addition unit that adds a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight after being reduced by the bit reduction unit to the convolution arithmetic unit.

The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.