A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

A resistive matrix computation circuit and methods for using the same are disclosed. In one embodiment, a resistive matrix computation circuit includes a memory configured to store a first set of operands and a second set of operands, where the first set of input operands and the second set of input operands are programmable by a controller, and the first set of operands and the second set of operands are cross-multiplied to form a plurality of product pairs, a plurality of resistive multiplier circuits configured to generate a plurality of output voltages according to the plurality of product pairs; the controller is configured to control the plurality of resistive multiplier circuits to perform multiplications using the first set of operands and the second set of operands, and an aggregator circuit configured to aggregate the plurality of output voltages from the plurality of resistive multiplier circuits, where the plurality of output voltages represent an aggregated value of the plurality of product pairs.

A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

Vector-vector multiplication or matrix-matrix multiplication computation on computing systems can include computing a first portion of a vector-vector multiplication product based on a most-significant-bit set of a first vector and a most-significant-bit set of a second vector, and determining if the first portion of the vector-vector multiplication product is less than a threshold. If the first partial vector-vector multiplication product is not less than the threshold, a remaining portion of the vector-vector multiplication product can be computed, and a rectified linear vector-vector multiplication product can be determined for the sum of the first portion of the vector-vector multiplication product and the remaining portion of the vector-vector multiplication product. If the first portion of the vector-vector multiplication product is less than the threshold, computation of the remaining portion of the vector-vector multiplication product can be skipped and the rectified linear vector-vector multiplication product can be set to a zero scalar.

Vector-vector multiplication or matrix-matrix multiplication computation on computing systems can include computing a first portion of a vector-vector multiplication product based on a most-significant-bit set of a first vector and a most-significant-bit set of a second vector, and determining if the first portion of the vector-vector multiplication product is less than a threshold. If the first partial vector-vector multiplication product is not less than the threshold, a remaining portion of the vector-vector multiplication product can be computed, and a rectified linear vector-vector multiplication product can be determined for the sum of the first portion of the vector-vector multiplication product and the remaining portion of the vector-vector multiplication product. If the first portion of the vector-vector multiplication product is less than the threshold, computation of the remaining portion of the vector-vector multiplication product can be skipped and the rectified linear vector-vector multiplication product can be set to a zero scalar.

A reservoir includes a common input layer, first and second output layers that outputs a first and a second readout values based on an input, a first partial reservoir including the input layer and the first output layer, and a second partial reservoir having a size between the input layer and the second output layer larger than the size of the first partial reservoir, and the training processing including: first calculating a third output weight that reduces a difference between a first product sum value of a third readout value and a first output weight; and second calculating a fourth output weight that reduces a difference between a second product sum value of a fourth readout value and a second output weight and differential teaching data that is a difference between a third product sum value of the third readout value and the third output weight and the teaching data.