Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines to use a prediction mode for coding (encoding/decoding) information associated with a current point in a point cloud. In the prediction mode, the information associated with the current point is predicted based on one or more neighbor points of the current point. The processing circuitry calculates, using integer operations, a distance-based weighted average value based on distances of the one or more neighbor points to the current point, and determines the information associated with the current point based on the distance-based weighted average value.

Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines to use a prediction mode for coding (encoding/decoding) information associated with a current point in a point cloud. In the prediction mode, the information associated with the current point is predicted based on one or more neighbor points of the current point. The processing circuitry calculates, using integer operations, a distance-based weighted average value based on distances of the one or more neighbor points to the current point, and determines the information associated with the current point based on the distance-based weighted average value.

The present disclosure concerns a method of executing a SoftMax function, the method comprising: (i) pre-storing in memory M fraction components (fc.sub.j) in binary form, derived from the expression 2.sup.(j/M), said fc.sub.j forming a lookup table (T) of size M; (ii) calculating, for each z.sub.i, an element y.sub.i of a number of the form 2.sup.y.sup.i; (iii) separating y.sub.i into an integral part (int.sub.i) and a fractional part (fract.sub.i); (iv) determining a lookup index (ind.sub.i) that corresponds to fract.sub.i scaled by the size M; (v) retrieving a fraction component fc.sub.i from T with ind.sub.i; (vi) generating, in a result register, a binary number representative of the exponential value of said z.sub.i, by combining said fc.sub.i retrieved from T and said int.sub.i; (v) adding the K result registers corresponding to z.sub.i into a sum register R7; and (vi) determining the K probability values p.sub.i from the K result registers and the sum register.

The present disclosure concerns a method of executing a SoftMax function, the method comprising: (i) pre-storing in memory M fraction components (fc.sub.j) in binary form, derived from the expression 2.sup.(j/M), said fc.sub.j forming a lookup table (T) of size M; (ii) calculating, for each z.sub.i, an element y.sub.i of a number of the form 2.sup.y.sup.i; (iii) separating y.sub.i into an integral part (int.sub.i) and a fractional part (fract.sub.i); (iv) determining a lookup index (ind.sub.i) that corresponds to fract.sub.i scaled by the size M; (v) retrieving a fraction component fc.sub.i from T with ind.sub.i; (vi) generating, in a result register, a binary number representative of the exponential value of said z.sub.i, by combining said fc.sub.i retrieved from T and said int.sub.i; (v) adding the K result registers corresponding to z.sub.i into a sum register R7; and (vi) determining the K probability values p.sub.i from the K result registers and the sum register.

A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

An exponential calculator based on parallel computing is disclosed. The exponential calculator includes a master system and a plurality of nodes interconnected with each other to transfer and receive information and perform sub-computations independently and simultaneously. The master system is configured to select a number of nodes from the plurality of nodes required to perform sub-computations for calculation of an integer exponent. The selected nodes is configured to receive value of a node base and a node exponent from the master system. The selected nodes calculate a first computation value, a second computation value and a third computation value. The master system is further configured to instruct a sub-set of the selected nodes to perform summation of a final sub-computation of the selected nodes and provide an output.

An exponential calculator based on parallel computing is disclosed. The exponential calculator includes a master system and a plurality of nodes interconnected with each other to transfer and receive information and perform sub-computations independently and simultaneously. The master system is configured to select a number of nodes from the plurality of nodes required to perform sub-computations for calculation of an integer exponent. The selected nodes is configured to receive value of a node base and a node exponent from the master system. The selected nodes calculate a first computation value, a second computation value and a third computation value. The master system is further configured to instruct a sub-set of the selected nodes to perform summation of a final sub-computation of the selected nodes and provide an output.