A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.

Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.

Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.

A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A fixed logic circuit configured to perform a multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer. The fixed logic circuit includes division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

└2.sup.ix/q┘

where q,i are selected such that:

a*x=└2.sup.ix/q┘

Multiplication logic determines a predetermined number of one or more least significant bits of the result of the multiplication operation a*x; and output logic combines the predetermined number of one or more most significant bits of the result of the division operation with the predetermined number of one or more least significant bits of the result of the multiplication operation so as to provide an output for the multiplication operation a*x.