Systems and methods for improving correlation. In at least one system and method, a signal is received and divided into a plurality of slices. Each of the slices is divided into a plurality of sub-slices. A plurality of chips of a PN code are generated, and sub-slice correlation results are generated in parallel. Summation of the sub-slice correlation results generates a slice correlation results, and the accumulated slice correlation results provide a correlation result.

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

A computer implemented method for analyzing and verifying software for safety and security. A software program comprising a sequence of program statements to be executed is provided. A compact representation of the program is computed, and the subset of program statements that are relevant to a property of the software to be verified is identified. A homomorphism that maps non-relevant program statements to an identity is computed, and the property is verified using the homomorphism.

A computer implemented method for analyzing and verifying software for safety and security. A software program comprising a sequence of program statements to be executed is provided. A compact representation of the program is computed, and the subset of program statements that are relevant to a property of the software to be verified is identified. A homomorphism that maps non-relevant program statements to an identity is computed, and the property is verified using the homomorphism.

According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.

According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.