The present disclosure advantageously provides a mixed precision computation (MPC) unit for executing one or more mixed-precision layers of an artificial neural network (ANN). The MPC unit includes a multiplier circuit configured to input a pair of operands and output a product, a first adder circuit coupled to the multiplier circuit, a second adder circuit, coupled to the first adder circuit, configured to input a pair of operands, an accumulator circuit, coupled to the multiplier circuit and the first adder circuit, configured to output an accumulated value, and a controller, coupled to the multiplier circuit, the first adder circuit, the second adder circuit and the accumulator circuit, configured to input a mode control signal. The controller has a plurality of operating modes including a high precision mode, a low precision add mode and a low precision multiply mode.

A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number N.sub.d of bits, decomposing the sample into a plurality of binary words of parameterizable bit size N.sub.p, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient.

A secret share value [q] of a quotient q of a/p is obtained through secure computation using a secret share value [a] and a modulus p and [a/d.sub.0]=[(a+qp)/d.sub.0]−[q]p/d.sub.0, . . . , [a/d.sub.n−1 ]=[(a+qp)/d.sub.n−1]−[q]p/d.sub.n−1 are obtained and output through secure computation using secret share values [a] and [q], divisors d.sub.0, . . . , d.sub.n−1, and a modulus p. Here, [μ] is a secret share value of μ, a is a real number, n is an integer equal to or greater than 2, d.sub.0, . . . , d.sub.n−1 are divisors of real numbers, p is a modulus of a positive integer, and q is a quotient of a positive integer.

A secret share value [q] of a quotient q of a/p is obtained through secure computation using a secret share value [a] and a modulus p and [a/d.sub.0]=[(a+qp)/d.sub.0]−[q]p/d.sub.0, . . . , [a/d.sub.n−1 ]=[(a+qp)/d.sub.n−1]−[q]p/d.sub.n−1 are obtained and output through secure computation using secret share values [a] and [q], divisors d.sub.0, . . . , d.sub.n−1, and a modulus p. Here, [μ] is a secret share value of μ, a is a real number, n is an integer equal to or greater than 2, d.sub.0, . . . , d.sub.n−1 are divisors of real numbers, p is a modulus of a positive integer, and q is a quotient of a positive integer.

Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

The subject matter described herein provides systems and techniques for the design and use of multiply-and-accumulate (MAC) units to perform matrix multiplication by systolic arrays, such as those used in accelerators for deep neural networks (DNNs). These MAC units may take advantage of the particular way in which matrix multiplication is performed within a systolic array. For example, when a matrix A is multiplied with a matrix B, the scalar value, a, of the matrix A is reused many times, the scalar value, b, of the matrix B may be streamed into the systolic array and forwarded to a series of MAC units in the systolic array, and only the final values and not the intermediate values of the dot products, computed for the matrix multiplication, may be correct. MAC unit hardware that is particularized to take advantage of these observations is described herein.

The present invention relates to convolution neural networks (CNN) and methods for improving computational efficiency of multiply accumulate (MAC) array structure Specifically, the invention relates to cutting of activation data into a number of tiles for increasing overall computation efficiency. The invention discloses techniques to cut an activation data into a plurality of tiles by using a 3-D convolution computation core and support bigger tensor sizes. Lastly, the invention provides adaptive scheduling of MAC array to achieve high utilization in multi-precision neural network acceleration.

According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

Methods and devices for simplifying data collected from assets are provided. An example method involves obtaining raw data from a data source at an asset, determining whether a data logging trigger is satisfied, and, when satisfied, performing a dataset simplification algorithm on the raw data to generate a simplified set of data in which interpolation error is limited by an upper bound that is fixed across the simplified set of data.