A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an i.sup.th bit of the first input and a j.sup.th bit of the second input, output an operation value of an operation performed on the i.sup.th bit of the first input and the j.sup.th bit of the second input based on the determination, and produce an operation value of the operation based on the determination.

Described herein is a neural network accelerator with a set of neural processing units and an instruction set for execution on the neural processing units. The instruction set is a compact instruction set including various compute and data move instructions for implementing a neural network. Among the compute instructions are an instruction for performing a fused operation comprising sequential computations, one of which involves matrix multiplication, and an instruction for performing an elementwise vector operation. The instructions in the instruction set are highly configurable and can handle data elements of variable size. The instructions also implement a synchronization mechanism that allows asynchronous execution of data move and compute operations across different components of the neural network accelerator as well as between multiple instances of the neural network accelerator.

Described herein is a neural network accelerator with a set of neural processing units and an instruction set for execution on the neural processing units. The instruction set is a compact instruction set including various compute and data move instructions for implementing a neural network. Among the compute instructions are an instruction for performing a fused operation comprising sequential computations, one of which involves matrix multiplication, and an instruction for performing an elementwise vector operation. The instructions in the instruction set are highly configurable and can handle data elements of variable size. The instructions also implement a synchronization mechanism that allows asynchronous execution of data move and compute operations across different components of the neural network accelerator as well as between multiple instances of the neural network accelerator.

A method for diagnosing a vehicle electrical system of a vehicle including a plurality of intercommunicating arithmetic logic units. A diagnostic application is executed on one arithmetic logic unit of the plurality of arithmetic logic units. The diagnostic application receives a diagnostic inquiry from an external diagnostic unit. The diagnostic inquiry is analyzed by the diagnostic application. Based on the content of the diagnostic inquiry, the diagnostic application sends data to at least one arithmetic logic unit and/or sends a diagnostic response to the external diagnostic unit.

A method for diagnosing a vehicle electrical system of a vehicle including a plurality of intercommunicating arithmetic logic units. A diagnostic application is executed on one arithmetic logic unit of the plurality of arithmetic logic units. The diagnostic application receives a diagnostic inquiry from an external diagnostic unit. The diagnostic inquiry is analyzed by the diagnostic application. Based on the content of the diagnostic inquiry, the diagnostic application sends data to at least one arithmetic logic unit and/or sends a diagnostic response to the external diagnostic unit.

A method of performing computation using a hybrid quantum-classical computing system including a classical computer, a system controller, and a quantum processor includes identifying a computational problem to be solved and a quantum algorithm to be used to solve the computational problem, detecting one or more faulty two-qubit gates among a plurality of two-qubit gates that can be applied to pairs of qubits in the quantum processor, compiling a computational task to solve the computational problem based on the quantum algorithm into a series of logic gates, including single-qubit gates and two-qubit gates that exclude the detected one or more faulty two-qubit gates, executing the series of logic gates on the quantum processor, measuring one or more of the qubits in the quantum processor, and outputting a solution to the identified computational problem derived from the measured results of the one or more of the qubits in the quantum processor.

A method of performing computation using a hybrid quantum-classical computing system including a classical computer, a system controller, and a quantum processor includes identifying a computational problem to be solved and a quantum algorithm to be used to solve the computational problem, detecting one or more faulty two-qubit gates among a plurality of two-qubit gates that can be applied to pairs of qubits in the quantum processor, compiling a computational task to solve the computational problem based on the quantum algorithm into a series of logic gates, including single-qubit gates and two-qubit gates that exclude the detected one or more faulty two-qubit gates, executing the series of logic gates on the quantum processor, measuring one or more of the qubits in the quantum processor, and outputting a solution to the identified computational problem derived from the measured results of the one or more of the qubits in the quantum processor.

A neural network is trained to identify one or more features of an image. The neural network is trained using a small number of original images, from which a plurality of additional images are derived. The additional images generated by rotating and decoding embeddings of the image in a latent space generated by an autoencoder. The images generated by the rotation and decoding exhibit changes to a feature that is in proportion to the amount of rotation.

A neural network is trained to identify one or more features of an image. The neural network is trained using a small number of original images, from which a plurality of additional images are derived. The additional images generated by rotating and decoding embeddings of the image in a latent space generated by an autoencoder. The images generated by the rotation and decoding exhibit changes to a feature that is in proportion to the amount of rotation.

An arithmetic processing apparatus includes: a plurality of nodes (N nodes) capable of communicating with each other, each of the plurality of nodes including a memory and a processor, the memory being configured to store a value and an operation result, the processor being configured to execute first processing when N is a natural number of 2 or more, n is a natural number of 1 or more, and N≠2.sup.n, wherein the first processing is configured to divide by 2 a value held by a first node, the first node being any of the plurality of nodes and a last node in an order of counting, obtain one or more node pairs by pairing remaining nodes among the plurality of nodes exception for the first node, and calculate repeatedly an average value of values held by each node pair of the one or more node pairs.