A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.

A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n.sup.2.

A method for ascertaining a randomized digital data stream. The method includes ascertaining a first bit stream as a function of an analog input data stream; ascertaining a second randomized bit stream as a function of the first bit stream, the second randomized bit stream being ascertained in a non-periodic temporal sequence; ascertaining a first digital data stream as a function of the second randomized bit stream; ascertaining a second digital data stream including pseudo random numbers; and ascertaining the randomized digital data stream as a function of the first digital data stream and as a function of the second digital data stream.

A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations that involve a cryptographic permutation. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a cryptographic architecture is provided. The cryptographic architecture has a processor interface comprising a set of cryptographic registers, where the processor interface is accessible by at least one processing unit. The cryptographic architecture also has a cryptographic permutation unit comprising circuitry to perform a cryptographic permutation using data stored within the set of cryptographic registers. In examples, the at least one processing unit instructs the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface.

Apparatuses, systems, and techniques to descramble or scramble data use a graphics processing unit (GPU) to perform descrambling. For example, in at least one embodiment, generation of a descrambling sequence is distributed among GPU threads for parallel calculation of the descrambling sequence and/or descrambling is distributed among GPU threads for descrambling.

A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.

Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.

A MAC tag list generation apparatus, on reception of a nonce N unique value to each MAC generation process and a message M, generates a t×m group test matrix H serving as combinatorial group testing parameters for s (a positive integer) which is the number of the MACs to be generated, generates a MAC tag list T=(T[1], . . . , T[t]) by generating a MAC value T[i] corresponding to the i-th test (i=1, . . . , t) using the group test matrix H, the nonce N, and pseudorandom functions F and G with variable length input and fixed length output for the message M, and outputs the MAC tag list.