Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

Provided are a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence. The method may include generating, for an n-stage NLFSR that requires more than two taps to generate a maximal length pseudo-random sequence, a pseudo-random sequence using a feedback logical operation of only a first logic gate and a second logic gate. Two non-end taps suitable for providing an at least near-maximal length pseudo-random sequence are inputs for the first logic gate, an output of the first logic gate and an end tap are inputs for the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage NLFSR.

An optimization apparatus includes hardware circuits configured to function as a random number generator configured to operate either in a first operation mode in which to generate a random number sequence after performing an initialization or in a second operation mode in which to generate a random number sequence without performing the initialization, an annealing calculation unit configured to perform an annealing process by use of random numbers generated by the random number generator, and an operation instruct unit configured to cause the random number generator to start operating in the first operation mode when the annealing calculation unit starts the annealing process, to cause the random number generator to stop operating when the annealing calculation unit, suspends the annealing process, and to cause the random number generator to restart operating in the second operation mode when the annealing calculation unit restarts the annealing process.

A pseudo-random number generation circuit device includes a pseudo-random number generation circuit including a logic circuit configured based on rule data that generates a next random number value from a current random number value, a cycle detection circuit that detects, based on a seed, an end of a cycle of random numbers, which are generated by the pseudo-random number generation circuit, and a rule data generation circuit that generates new rule data at a first trigger, at which the cycle detection circuit detects the end of the cycle of random numbers, to output the new rule data to the pseudo-random number generation circuit, wherein the cycle detection circuit stores a random number value, which is generated by a new logic circuit configured based on the new rule data, as the seed.

This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.

A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.

A method, apparatus, and computer program product for improved pseudo-random number generation are provided. An example method includes receiving, by a computing device, a request for a pseudo-random number, selecting, by randomization circuitry of the computing device, a first attribute from a biometric attribute dataset, and obtaining a first value for the first attribute. The method further includes selecting, by the randomization circuitry, a second attribute, and obtaining a second value for the second attribute. The method includes convoluting, by convolution circuitry, the first value with the second value to generate the pseudo-random number.

A control flow attacks based on return address signatures comprises: using a return address as a push return address when a response is given to an interrupt service routine; generating an encrypted push return address by an XOR encryption circuit by means of an n-bit binary key generated by a pseudo random number generator; then, generating a push_address signature value by an MD algorithm signature circuit; when the response to the interrupt service routine is over, reading an n-bit binary address out of a stack to serve as a pop return address; generating an encrypted pop return address by the XOR encryption circuit; generating a pop address signature value by the MD algorithm signature circuit; comparing the push_address signature value with the pop address signature value; and determining whether or not a data processor is under a control flow attack according to a comparison result.

An emulation system may have a built-in self-test circuit to generate one or more built-in self-test instructions. The one or more built-in self-test instructions may be pseudorandom. The one or more built-in self-test instructions may cause one or more emulation processors of the emulation system to generate one or more deterministic outputs. A testing processor of the emulation system may compare the one or more deterministic outputs to detect a faulty emulation processor, a faulty emulation processor cluster, or a faulty emulation chip of the emulation system.