A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2.sup.m and a reduction modulo 2.sup.m1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2.sup.m multiply-and-accumulate operations and modulo 2.sup.m1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.

Performing processing using hardware counters in a computer system includes storing, in association with greatest common divisor (GCD) processing of the system, a first variable in a first redundant binary representation and a second variable in a second redundant binary representation. Each such redundant binary representation includes a respective sum term and a respective carry term, and a numerical value being represented by a redundant binary representation is equal to a sum of the sum and carry terms of the redundant binary representation. The process performs redundant arithmetic operations of the GCD processing on the first variable and second variables using hardware counter(s), of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form. The process uses output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing.

Provided are a security processor for performing a remainder operation by using a random number and an operating method of the security processor. The security processor includes a random number generator configured to generate a first random number; a modular calculator configured to generate a first random operand based on first data and the first random number and generate output data through a remainder operation on the first random operand, wherein a result value of the remainder operation on the first input data is identical to a result value of the remainder operation on the first random operand.

The present disclosure relates to an arrangement (200) for simulating a quantum Toffoli gate. The arrangement is arranged to receive at least first, second, third, fourth, fifth and sixth classical input bits (a, b, c, d, e, f) and arranged to output at least first, second, third, fourth, fifth and sixth classical output bits. The first, third and fifth classical output bits are arranged to simulate controlled-controlled-NOT, CCNOT, logic based on the first, third and fifth classical input bits (a, c, e). The second, fourth and sixth classical output bits are arranged to simulate phase kickback based on the first, second, third, fourth and sixth classical input bits (a, b, c, d, f). The present disclosure also relates to corresponding systems, methods and computer programs.

A hardware implementations of Montgomery modular multiplication are described. The number of components as well as the number of cycles may be reduced by using a lookup table and multiplexer for selecting terms to be added during calculations. Also a loop unrolling technique may be used improve performance. A chain of pipeline adder modules and a chain of delay and shift modules may be used to pipeline calculations of multiple sets of operands.

A multiplication and accumulation (MAC) operator includes a residue number generating circuit configured to generate a plurality of weight residue number data for weight data and a plurality of vector residue number data for the vector data by using a plurality of divisors, a multiplication circuit configured to generate a plurality of residue number multiplication data by performing a multiplication operation on the weight residue number data and the vector residue number data, an addition circuit configured to generate residue number multiplication addition data by performing an addition operation on the multiplication data, an accumulating circuit configured to generate residue number accumulation data by performing an accumulation operation on the residue number multiplication addition data and latch data, and a mixed radix conversion circuit configured to generate the MAC result data by using the divisors and the residue number accumulation data that is transmitted by the accumulating circuit.

An integrated circuit may be provided with a modular multiplication circuit. The modular multiplication circuit may include an input multiplier for computing the product of two input signals, truncated multipliers for computing another product based on a modulus value and the product, a subtraction circuit for computing a difference between the two products. An error correction circuit may use the difference to look up an estimated quotient value and to subtract out an integer multiple of the modulus value from the difference in a single step, wherein the integer multiple is equal to the estimated quotient value. A final adjustment stage may be used to remove any remaining residual estimation error.

Embodiments of the present disclosure provide a data processing method and apparatus, wherein the data processing method includes: determining a first matrix and a second matrix, and splitting the second matrix into a first preset quantity of matrix blocks; invoking a Montgomery modular multiplication and addition instruction to perform an operation on an element included in the first matrix and an element included in a j.sup.th matrix block to obtain a matrix block operation result corresponding to the j.sup.th matrix block, and covering the element in the j.sup.th matrix block with the matrix block operation result corresponding to the j.sup.th matrix block; and increasing j by 1, continuing to perform the above-described step of obtaining the matrix block operation result until j is equal to the first preset quantity so as to obtain a target matrix from the matrix multiplication operation performed on the first matrix and the second matrix. In this way, a high-performance matrix multiplication algorithm based on Montgomery modular multiplication and addition is provided, which reduces operational complexity, effectively uses the advantages of batch processing of the Montgomery modular multiplication and addition instruction, and improves the operation efficiency of a processor performing a matrix multiplication operation.

A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

A multiplication unit includes first, second, third and fourth receiving terminals, arithmetic units and multiplexers. In complex number mode, the first and second receiving terminals receive a real part value and an imaginary part value of a first complex number, respectively, whereas the third and fourth receiving terminals receive a real part value and an imaginary part value of a second complex number, respectively. In modulus mode, the first and third receiving terminals receive first and second integers, respectively. The multiplexers gate the arithmetic units to perform a complex number multiplication operation according to the first and second complex numbers to generate a third complex number in complex number mode and perform a modulus multiplication operation according to the first and second integers and a predetermined modulus to generate a third integer in modulus mode.