A crypto processor, a method of operating a crypto processor, and an electronic device including a crypto processor. A method of operating a crypto processor for performing a polynomial multiplication of lattice-based texts includes transferring coefficients of polynomials for the polynomial multiplication to multipliers, performing multiplications for a portion of the coefficients in parallel using the multipliers, performing an addition for a portion of results of the multiplications using an adder, and determining a result of the polynomial multiplication based on another portion of the results of the multiplications and a result of the addition.

A radar system includes transmitters and receivers configured for installation and use in a vehicle. The transmitters transmit radio signals. The receivers receive radio signals that include the transmitted radio signals reflected from objects in an environment. Each receiver has a controller, a buffer, and a post-buffer processor. The receiver processes the received radio signals and stored data samples in the buffer. The buffer operates in a plurality of modes defined by the controller. Two or more modes of operation of the plurality of modes are performed with a same set of data samples stored in the buffer. The post-buffer processor receives data samples from the buffer and performs at least one of correlation processing to determine object ranges, Doppler processing to determine object velocity, and, in combination with other receivers of the plurality of receivers, further processing to determine angular locations of the objects.

Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n.sup.2.

A radar sensing system includes a plurality of transmitters configured to transmit radio signals and a plurality of receivers configured to receive radio signals. First and second transmitters of the plurality of transmitters are configured to generate radio signals defined by first and second spreading code chip sequences, respectively. A first receiver of the plurality of receivers processes received radio signals as defined by a plurality of spreading code chip sequences that includes at least the first and second spreading code chip sequences. The radar sensing system also includes a code generator for generating the spreading code chip sequences.

A method for creating unified, efficient hardware implementations for multiple symmetric ciphers is described. For a chosen set of two or more distinct types of symmetric ciphers, a unified substitution box (SBOX) is designed that can implement most of the operations in a single hardware block, with small hardware blocks added before and after the unified SBOX for unique operations of each distinct symmetric cipher. Optimization techniques can also be applied to the linear operations and SBOX operations for the chosen set, rather than individually for each symmetric cipher, of the two or more distinct types of symmetric ciphers.

According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations.

A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

Combined post-quantum security utilizing redefined polynomial calculation is described. An example of an apparatus includes a first circuit for key encapsulation operation; a second circuit for digital signature operation; and a NTT (Number Theoretic Transform) multiplier circuit, wherein the NTT multiplier circuit provides for polynomial multiplication for both the first circuit and the second circuit, wherein the apparatus is to remap coefficients of polynomials for the first circuit to a prime modulus for the second circuit, and perform polynomial multiplication for the first circuit utilizing the remapped coefficients of the polynomials for the first circuit.

A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of F.sub.p.sup.2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

A radar system includes transmitters and receivers. The transmitters transmit radio signals. The receivers receive radio signals that include the transmitted radio signals reflected from objects in an environment. Each receiver has a controller, a buffer, and a post-buffer processor. The receiver processes the received radio signals and stored data samples in the buffer. The buffer operates in a plurality of modes defined by the controller. Modes of operation are selected for each of the respective buffers. Each buffer's mode of operation is selected to perform a desired processing on respective data samples. Each of the post-buffer processors receive their respective data samples from the respective buffers and performs further data processing on the respective data samples.