In a process of taking a first square matrix formed from elements of a finite field as input and obtaining at least some of entries of a second square matrix which includes an upper triangular portion resulting from triangulation of the first square matrix, product-sum operation is performed on entries as operands at multiple positions in a matrix which is based on the first square matrix to obtain a product-sum operation result corresponding to an entry at a different position than the operands, and reduction of the product-sum operation result is performed.

A radar sensing system for a vehicle has multiple transmitters and receivers on a vehicle. The transmitters are configured to transmit radio signals which are reflected off of objects in the environment. There are one or more receivers that receive the reflected radio signals. Each receiver has an antenna, a radio frequency front end, an analog-to-digital converter (ADC), and a digital signal processor. The transmitted signals are based on spreading codes generated by a programmable code generation unit. The receiver also makes use of the spreading codes generated by the programmable code generation unit. The programmable code generation unit is configured to selectively generate particular spreading codes that have desired properties.

For example, the present techniques may provide an energy-efficient multipurpose encryption engine capable of processing both AES and CRC algorithms using a shared Galois Field Computation Unit (GFCU). In an embodiment, an apparatus may comprise computation circuitry adapted to perform Galois Field computations and control circuitry adapted to control the computation circuitry so as to selectively compute either an Advanced Encryption Standard cipher or a Cyclic Redundancy Check.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

A radar sensing system for a vehicle includes transmitters, receivers, a memory, and a processor. The transmitters transmit radio signals and the receivers receive reflected radio signals. The processor produces samples by correlating reflected radio signals with time-delayed replicas of transmitted radio signals. The processor stores this information as a first radar data cube (RDC), with information related to signals reflected from objects as a function of time (one of the dimensions) at various distances (a second dimension) for various receivers (a third dimension). The first RDC is processed to compute velocity and angle estimates, which are stored in a second RDC and a third RDC, respectively. One or more memory optimizations are used to increase performance. Before storing the second RDC and the third RDC in an internal/external memory, the second and third RDCs are sparsified to only include the outputs in specific regions of interest.

Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an nk generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belongin some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.

A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2.sup.m and a reduction modulo 2.sup.m1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2.sup.m multiply-and-accumulate operations and modulo 2.sup.m1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.

A radar sensing system for a vehicle has multiple transmitters and receivers on a vehicle. The transmitters are configured to transmit radio signals which are reflected off of objects in the environment. There are one or more receivers that receive the reflected radio signals. Each receiver has an antenna, a radio frequency front end, an analog-to-digital converter (ADC), and a digital signal processor. The transmitted signals are based on spreading codes generated by a programmable code generation unit. The receiver also makes use of the spreading codes generated by the programmable code generation unit. The programmable code generation unit is configured to selectively generate particular spreading codes that have desired properties.

Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.

Some embodiments are directed to an electronic computation device (100) arranged for obfuscated execution of a multiplication. The device comprises a storage (120) arranged for storing multiple variables used in the execution of an arithmetic operation, a variable (x: y; 2) of the multiple variables being represented as multiple multiplicative shares (X=(x.sub.0, x.sub.1, . . . , x.sub.m1); Y=(y.sub.0, y.sub.1, . . . , y.sub.m1); 20), said multiplicative shares being represented in the storage as multiple additive shares (x.sub.i=(x.sub.i,0,x.sub.i,1, . . . , x.sub.i,n1); Yi=(y.sub.i,0,y.sub.i,1, . . . , y.sub.i,n1); 210, 220).