Disclosed is a ciphertext computation method. The ciphertext computation method includes: receiving a modular computation command for a plurality of ciphertexts; performing a modular computation for the plurality of ciphertexts by using a lookup table storing a plurality of predetermined prime number information; and outputting a result of the computation.

When an absolute value of a difference value between a first share and a second share which are secret-shared is less than or equal to a natural number t, the information processing apparatus calculates the difference value between the first share and the second share. Furthermore, the information processing apparatus performs a comparison in magnitude of the first share and the second share using bit-decomposition from a least significant bit to an m-th bit (m being a natural number) of the difference value.

A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2.sup.m and a reduction modulo 2.sup.m1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2.sup.m multiply-and-accumulate operations and modulo 2.sup.m1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.

The present disclosure discloses a file storing method which comprises: when a file storing instruction being received, determining a file name corresponding to the file to be stored; performing feature calculation on the determined file name to obtain a feature value; performing modulo operation to the feature value using the total number of file directories to obtain a modulus value, wherein the modulo operating is carried out by dividing the total number of the file directories by the feature value; determining a serial number corresponding to the file name based on the modulus value; and based on a mapping relationship between a preset serial number and a directory, determining the directory corresponding to the serial number, and storing the file in the determined directory. The present disclosure further discloses a terminal and a computer-readable storage medium. The flexibility of file storing is improved and the use of the directories is more balanced.

This disclosure relates to data encryption and decryption. In one aspect, a method includes receiving, by a second peer end computing device, first data from a first peer end computing device. The second end computing device generates a random term based on a result range pre-agreed upon with the first peer end computing device. The result range includes a minimum result value and a maximum result value. The random term is a product of a random number and an agreed upon constant. The agreed upon constant is greater than a difference between the maximum result value and the minimum result value. The second peer end computing device performs a homomorphic operation based on the first data, local private second data, and the random term to obtain an encryption result. The second peer end computing device returns the encryption result to the first peer end computing device.

The present disclosure relates to an arrangement (200) for simulating a quantum Toffoli gate. The arrangement is arranged to receive at least first, second, third, fourth, fifth and sixth classical input bits (a, b, c, d, e, f) and arranged to output at least first, second, third, fourth, fifth and sixth classical output bits. The first, third and fifth classical output bits are arranged to simulate controlled-controlled-NOT, CCNOT, logic based on the first, third and fifth classical input bits (a, c, e). The second, fourth and sixth classical output bits are arranged to simulate phase kickback based on the first, second, third, fourth and sixth classical input bits (a, b, c, d, f). The present disclosure also relates to corresponding systems, methods and computer programs.

A hardware implementations of Montgomery modular multiplication are described. The number of components as well as the number of cycles may be reduced by using a lookup table and multiplexer for selecting terms to be added during calculations. Also a loop unrolling technique may be used improve performance. A chain of pipeline adder modules and a chain of delay and shift modules may be used to pipeline calculations of multiple sets of operands.

In an aspect, an apparatus obtains at least a first input value and a second input value from a sender device. The apparatus performs a computational operation between portions of the first input value and portions of the second input value to obtain a plurality of partial results of the computational operation. The apparatus applies a hash function to each of the plurality of partial results of the computational operation to obtain a hash of a final result of the computational operation between the first input value and the second input value. The apparatus obtains the final result of the computational operation from the sender device. The apparatus verifies that the final result of the computational operation from the sender device is correct based on the hash of the final result of the computational operation.

A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M1 modulo units of the logarithmic tree provide x[0: m] mod d for all m{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of log.sub.2 M; and more than M2.sup.u of the subset of modulo units are arranged at the maximal delay of log.sub.2 M, where 2.sup.u is the power of 2 immediately smaller than M.

A processor of an aspect includes a plurality of registers, and a decode unit to decode an instruction. The instruction is to indicate at least one storage location that is to store a first integer, a second integer, and a modulus. An execution unit is coupled with the decode unit, and coupled with the plurality of registers. The execution unit, in response to the instruction, is to store a Montgomery multiplication product corresponding to the first integer, the second integer, and the modulus, in a destination storage location. Other processors, methods, systems, and instructions are disclosed.