Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

A digital encrypting and decrypting unit (PMEU) that operates according to a Rivest-Shamir-Adleman (RSA) cryptosystem based on Residue Numeral System (RNS) and Chinese Reminder Theorem (CRT). The unit includes two modular exponentiation calculating units (MES-1, MES-2) to process a two residual signals (X mod p; X mod q) to calculate a result of a modular exponentiation by a binary method. The calculating units have inputs (I-k[i], I-SM, I-MM) and outputs (O-k[i], O-SM, O-MM) for signals representing partial results of the modular exponentiation. A modular exponentiation controlling unit (MECU) is connected to the inputs and outputs of the calculating units to control flow of the signals representing the partial results of the modular exponentiation.

An electronic calculating device (100) arranged to convert an input number (y) represented ((y.sub.1, y.sub.2, . . . , y.sub.k)) m a residue number system (RNS) to an output number represented in a radix representation ((e.sub.0, e.sub.1, . . . e.sub.s1)), the calculating device comprising an input interface (110) arranged to receive the input number (y) represented in the residue number system, and a processor circuit (120) configured to iteratively update an intermediate number () represented in the residue number system, wherein iterations produce the digits (e.sub.0, e.sub.1, . . . e.sub.s1) in the radix representation with respect to the bases (b.sub.0, b.sub.1, . . . , b.sub.s1), at least one iteration comprises computing the intermediate number modulo a base (b.sub.t) of the radix representation to obtain a digit (e.sub.t=().sub.bt) of the radix representation, updating the intermediate number ((e.sub.t+F)/b.sub.t) by subtracting the digit from the intermediate number, adding an obfuscating number (F; F.sub.t), and dividing by the base (b.sub.t).

An integrated photonics computing system implements a residue number system (RNS) to achieve orders of magnitude improvements in computational speed per watt over the current state-of-the-art. RNS and nanophotonics have a natural affinity where most operations can be achieved as spatial routing using electrically controlled directional coupler switches, thereby giving rise to an innovative processing-in-network (PIN) paradigm. The system provides a path for attojoule-per-bit efficient and fast electro-optic switching devices, and uses them to develop optical compute engines based on residue arithmetic leading to multi-purpose nanophotonic computing.

A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2? radians, the photonic processor performs addition modulo 2?. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

A k-cluster residue number system has a processor and a memory. The processor is used to generate an addition and subtraction look-up table and a multiplication look-up table based on periodic behaviors of the modulo to compress the sizes of the addition and subtraction look-up table and the multiplication look-up table. The addition and subtraction look-up table has 2m.sub.i cells for recording values from zero to (m.sub.i?1) in an ascending order twice, wherein m.sub.i is a coprime integer of a modular set of the k-cluster residue number system. The multiplication look-up table has S cells, where

[00001]$S=\left(\frac{m_i^2-1}{4}\right).$

A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.

A modulo divider and a modulo division operation method for binary data are provided, including: converting a first variant and a second variant to a variant set according to a first mapping table; generating a fifth variant and a sixth variant according to the variant set; generating a seventh variant and an eighth variant according to the variant set; updating the first variant according to one of the fifth variant and the sixth variant and updating the second variant according to the other one of the fifth variant and the sixth variant; updating the third variant according to one of the seventh variant and the eighth variant and updating the fourth variant according to the other one of the seventh variant and the eighth variant; and outputting the third variant as a result of a modulo division operation in response to determining the updating of the third variant being finished.

A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.