Patent classifications
G06F8/311
REPRESENTATION AND ANALYSIS OF WORKFLOWS USING ABSTRACT SYNTAX TREES
A workflow for an operational process may be defined using a functional programming language. A computer system may parse the workflow to generate an abstract syntax tree, which may include states of the workflow and transitions from one workflow state to another. The computer system may generate code paths from the abstract syntax tree representing sequences of execution. Reflection on the workflow may be performed using the abstract syntax tree and code paths to allow intelligent decision-making.
Functional Method for Universal Computation by Extended Formal Matrix Product
Functional Method for Universal Computation by Extended Formal Matrix Product. The invention targets central processing units (1) that can be programmed by functional software devices (3) relying on the sole notion of application, (6) to (10), without any set of instructions whose complex sequential decoding is opposed to a parallelism independent of the software devices themselves (3), allowing, by the product (5) of binary matrices (2), a first parallelism said technical (24), autonomous and independent of functional algorithms, nevertheless performing these latter in a parallel way independently of their initial description (3). A second parallelism, said applicative, constituted by binary diagonally matrix (4) extended with indexes (13) situated inside the technical parallelism (2), performs simultaneously several tasks (4), always without instructions, nor task scheduler. The method is constituted of an extended matrix product operation (24) on two set of memory words, (13) to (16), representing two triangular matrix (2), such that one allows to write the result of the product of its opposite (extended to a square matrix) by itself and reciprocally (2), according to three phases, called application (A), expansion (E) and reduction (R). The results are expressed by some binary connections (24) defined by the binary product between lines and columns. The software devices are vectors (17) of sequences of binary diagonally matrix (4) extended with index words (13) for each dimension, referring to positions into the software device (17). The method according to the invention is particularly intended to formal intrinsic computations (6), in computer science and in cognitive semantic.
METHOD FOR APPLICATION BUILDING
A method of generating an application by using an artificial neural network model includes a data processing step of pre-processing training data, a model training step of training the artificial neural network model based on the preprocessed training data, and an application making step of receiving an input for editing one or more components included in the application and an input for setting a connection relationship between the one or more components. The one or more components include the artificial neural network model.
Artificial intelligence engine with enhanced computing hardware throughput
An artificial intelligence (“AI”) engine is disclosed with AI-engine modules and a plurality of learning agents. The AI-engine modules include instructor, learner, and predictor modules. The learner module is configured to train a plurality of AI models in parallel, and the instructor module is configured to coordinate with a plurality of simulators for respectively training the AI models. The learning agents are configured to process training requests from the instructor on data from the simulators for training the AI models. The learner module is further configured to first train the AI models on a first batch of similar data synchronously pooled in a memory of the learner module with a first processor. The learner module is further configured to subsequently train the AI models on a second, different batch of similar data synchronously pooled in the memory of the learner module with the first processor.
SYSTEMS, METHODS AND MEDIA FOR DYNAMICALLY SHAPED TENSORS USING LIQUID TYPES
Systems, methods, and processor readable media are described for verifying software. A liquid type system is used by a programming language to allow source code to define tensor variables with dimensionality and/or shape dynamically defined at runtime. The dimensionality and shape of a tensor variable invoked in the source code, as well as the data type of the constituent elements of such a tensor variable, may be defined by a static type that may be verified at compile time.
Representation and analysis of workflows using abstract syntax trees
A workflow for an operational process may be defined using a functional programming language. A computer system may parse the workflow to generate an abstract syntax tree, which may include states of the workflow and transitions from one workflow state to another. The computer system may generate code paths from the abstract syntax tree representing sequences of execution. Reflection on the workflow may be performed using the abstract syntax tree and code paths to allow intelligent decision-making.
Automated creation, testing, training, adaptation and deployment of new artificial intelligence (AI) models
Functionality is provided for the automated creation, testing, training, adaptation and deployment of AI models and changes thereto. Base classes are provided that enable practicable creation of new models from existing one. New models are tested on live data sets offline from user sites. New training methods are provided for the production of particular outcomes. Efficient adaptation of new AI models is facilitated, encompassing data scientist and development team control over how fast to train and deploy new models.
Artificial intelligence engine for mixing and enhancing features from one or more trained pre-existing machine-learning models
An AI engine having an architect module to create a number of nodes and how the nodes are connected in a graph of concept nodes that make up a resulting AI model. The architect module also creates a first concept node by wrapping an external entity of code into a software container with an interface configured to exchange information in a protocol of a software language used by the external entity of code. The architect module also creates a second concept node derived from its description in a scripted file coded in a pedagogical programming language, and connects the second concept node into the graph of nodes in the resulting AI model.
Static and automatic inference of inter-basic block burst transfers for high-level synthesis
Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.
STATIC AND AUTOMATIC INFERENCE OF INTER-BASIC BLOCK BURST TRANSFERS FOR HIGH-LEVEL SYNTHESIS
Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.