A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

A task graph debranching section (109) determines as a parallelizable number, the number of parallelization of processes which is possible at a time of executing a program. A schedule generation section (112) generates as a parallelization execution schedule, an execution schedule of the program at the time of executing the program. A display processing section (114) computes a parallelization execution time which is a time required for executing the program at a time of executing the program according to the parallelization execution schedule. Further, the display processing section (114) generates parallelization information indicating the parallelizable number, the parallelization execution schedule, and the parallelization execution time, and outputs the generated parallelization information.

A multi-threaded imperative programming language includes language constructs that map to circuit implementations. The constructs can include a condition statement that enables a thread in a hardware pipeline to wait for a specified condition to occur, identify the start and end of a portion of source code instructions that are to be executed atomically, or indicate that a read-modify-write memory operation is to be performed atomically. Source code that includes one or more constructs mapping to a circuit implementation can be compiled to generate a circuit description. The circuit description can be expressed using hardware description language (HDL), for instance. The circuit description can, in turn, be used to generate a synchronous digital circuit that includes the circuit implementation. For example, HDL might be utilized to generate an FPGA image or bitstream that can be utilized to program an FPGA that includes the circuit implementation associate with the language construct.

A method and an apparatus that execute a parallel computing program in a programming language for a parallel computing architecture are described. The parallel computing program is stored in memory in a system with parallel processors. The parallel computing program is stored in a memory to allocate threads between a host processor and a GPU. The programming language includes an API to allow an application to make calls using the API to allocate execution of the threads between the host processor and the GPU. The programming language includes host function data tokens for host functions performed in the host processor and kernel function data tokens for compute kernel functions performed in one or more compute processors, e.g., GPUs or CPUs, separate from the host processor.

The present disclosure relates to data flow processing methods and devices. One example method includes obtaining a dependency relationship and an execution sequence of operating a data flow by a plurality of processing units, generating synchronization logic based on the dependency relationship and the execution sequence, and inserting the synchronization logic into an operation pipeline of each of the plurality of processing unit to generate executable code.

Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.

Various embodiments include systems and methods of operating the systems that include operation of a plurality of first nodes and second nodes in response to a request, where each first node is a first type of processing unit and each second node is a second type of processing unit, where the second type of processing node is different from the first type of processing node. Each of the first and second nodes can be operable in parallel with the other nodes of their respective plurality. Each second node may be operable to respond to the request using data and/or metadata it holds and/or operable in response to data and/or metadata from one or more of the first nodes. Additional apparatus, systems, and methods are disclosed.

A system and method for performing large-scale data processing using a statistical programming language are disclosed. One or more high-level statistical operations may be received. The received high-level statistical operations may be dynamically translated into a graph of low-level data operations. The unnecessary operations may be removed and operations may be fused or chained together. Operations may then be grouped into distributed data processing operation. The low-level operations may then be run.

A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.