A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

The present disclosure relates to data flow processing methods and devices. One example method includes obtaining a dependency relationship and an execution sequence of operating a data flow by a plurality of processing units, generating synchronization logic based on the dependency relationship and the execution sequence, and inserting the synchronization logic into an operation pipeline of each of the plurality of processing unit to generate executable code.

A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

A mobile application development device having a platform processor, a native application converter engine, and a mobile platform framework engine configured to facilitate the development and deployment of mobile applications configured to be run on different mobile operating systems from code that is developed independently and agnostic of the mobile operating system on which it will ultimately run.

A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

The present invention discloses a method of flow control in a computing device, for processing of flow control statements to adapt a data structure of a program running on the computing device and a computer program product storing the method. The invention thereby allows the integration of the kernels into the main program when compiling. The whole parsing of the CPU program parts and the kernels is done by 10 one single standard compiler. The actual compiler for the device can be linked as a library and does not need to do any parsing. The invention further allows loops and if-clauses to be used in language-embedded GPGPU programming, enabling full general-purpose programming of the device in a way that is fully embedded in an ordinary programming language. The device can be a highly parallel computing 15 device, such as a video card, or some other computing device.

A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

System and method for creating a machine vision application. A machine vision prototype comprising a plurality of machine vision steps specifying a machine vision image processing algorithm and associated parameters may be stored. The steps may be interpretable by an emulator to perform the specified image processing on an image by emulating or simulating execution of the steps on a hardware accelerator, e.g., a programmable hardware element or graphics processing unit. An emulator may emulate or simulate execution of the steps on the hardware accelerator, thereby generating image processing results, which may be displayed for validation of the emulating or simulating by a user. The prototype may be analyzed, and based on the analyzing, an estimate of resource usage or performance of the image processing algorithm for the hardware accelerator may be determined and displayed, and may be usable for target platform selection or modification of the image processing algorithm.

System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining.