Patent classifications
G06F8/44
Arithmetic enhancement of C-like smart contracts for verifiable computation
A system converts high level source code into an arithmetic circuit that represents the functionality expressed in the source code, such as a smart contract as used in relation to a blockchain platform. The system processes a portion of high level source code to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code.
Pathname independent probing of binaries
A system includes one or more processors in communication with a memory and configured to receive a task to probe a portion of the memory associated with a version of a binary file during execution of the binary file. The task includes a portion of object code and a hash identifier, both associated with the version of the binary file. A database mapping hash identifiers to debug information associated with installed binary files is accessed. Debug information for the version of the binary file associated with the hash identifier is retrieved. A probing application is built using the debug information and the portion of object code. Upon execution of the version of the binary file, the probing application places the object code into the portion of the memory.
MUTATION TESTING IN PARALLEL THREADS
Mutation testing can indicate whether mutants of a software application, created by intentionally altering source code of the software application, are successfully “killed” by test cases executed against the mutants. Mutation testing can be performed via parallel threads by, within each parallel thread, modifying individual source code class files and recompiling the modified class files to generate and test mutants. Individual mutation test results produced within each of the parallel threads can be aggregated to generate an aggregated test result report that indicates overall testing metrics associated with the mutation testing across the parallel threads.
CACHING OF COMPILED SHADER PROGRAMS IN A CLOUD COMPUTING ENVIRONMENT
Apparatuses, systems, and techniques for caching of compiled shader programs in a cloud computing environment.
SYNTHESIS FLOW FOR DATA PROCESSING ENGINE ARRAY APPLICATIONS RELYING ON HARDWARE LIBRARY PACKAGES
Implementing an application for a data processing engine (DPE) array can include detecting, using computer hardware, a component of a hardware library package instantiated by an application. The application is specified in source code and is configured to execute on a DPE array. An instance of the component is extracted from the application. The extracted instance specifies values of parameters for the instance of the component. The instance can be partitioned by generating program code defining one or more kernels corresponding to the instance of the component. The partitioning is based on a defined performance metric of the component and a defined performance requirement of the application. The application is transformed by replacing the instance of the component with the program code generated by the partitioning. The application, as transformed, is compiled into program code executable by the DPE array.
AI DIFFERENTIATION BASED HW-OPTIMIZED INTELLIGENT SOFTWARE DEVELOPMENT TOOLS FOR DEVELOPING INTELLIGENT DEVICES
A method of providing intelligent software is provided. According to the present disclosure, it is possible to request an optimal AI model on the basis of a pre-trained AI model and meta information of the AI model, and it is possible to easily provide an AI model optimized for an intelligence device by responding to the request by creating a plurality of AI differentiation models from the AI model in accordance with a plurality of differentiation levels.
System and method for developing, testing and debugging software for microcontrollers
Various implementations of the invention develop executable code for an embedded system, including a microcontroller and a device. Some implementations of the invention comprise a microcontroller development tool configured to operate on a general purpose computer. In some implementations, the development tool comprises: 1) a virtual microcontroller configured to operate within the development tool in a manner substantially identical to an operation of the microcontroller of the embedded system, wherein the virtual microcontroller operates within the development tool using op codes native to that of the microcontroller, the virtual microcontroller further configured to receive inputs from and provide outputs to the device of the embedded system, 2) an expanded memory beyond a memory available to the microcontroller, the expanded memory available to the virtual microcontroller and configured to store op codes or data for the virtual microcontroller to assist with development of executable code, and 3) a microcontroller programmer configured to transfer executable code to a memory of the microcontroller, wherein the executable code is developed within the development tool; and a microcontroller coupler configured to couple the development tool to the embedded system.
DYNAMIC MULTIPLE REPOSITORY PACKAGE MANAGEMENT THROUGH CONTINUOUS INTEGRATION
In one implementation, a method includes receiving data characterizing a notification indicative of modification to a first source code of a first layer of a software architecture. The first layer is stored in a first repository of a plurality of repositories of a microservice. The method further includes generating a modified first package including a first computer-executable code generated by at least compiling the first source code and assigning a unique first name to the modified first package. The method further includes transmitting an instruction to a repository manager of a package repository to store the modified first package with the assigned first name in the package repository. The method also includes generating a first modified container image including the modified first package.
Breakpoints in neural network accelerator
Techniques are disclosed for setting a breakpoint for debugging a neural network. User input is received by a debugger program executable by a host processor indicating a target layer of a neural network at which to halt execution of the neural network. The neural network includes a first set of instructions to be executed by a first execution engine and a second set of instructions to be executed by a second execution engine. A first halt point is set within the first set of instructions and a second halt point is set within the second set of instructions. It is then determined that operation of the first execution engine and the second execution engine has halted. It is then determined that the first execution engine has reached the first halt point. The second execution engine is then caused to move through instructions until reaching the second halt point.
Method and apparatus for generating metadata by a compiler
A method includes receiving a high-level function in a high-level code of an application is received. The method also include identifying resources in a hardware to execute a set of low-level instructions that is generated from the high-level function in the high-level code. One or more processing operations are determined to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The high-level function in the high-level code of the application is compiled into the set of low-level instructions to be executed on the hardware. A plurality of structured metadata is generated and includes information associated with the determining resources in the hardware and further includes information associated with the determining one or more processing operations.