A method comprises: compiling the code segment with a compiler; and determining, based on an intermediate result of the compiling, a resource associated with a dedicated processing unit and for executing the code segment. As such, the resource required for executing a code segment may be determined quickly without actually executing the code segment and allocating or releasing the resource, which helps subsequent resource allocation and further brings about a better user experience.

An example embodiment may involve obtaining one or more blueprint files. The blueprint files may collectively define a system of processing nodes, a call flow involving a sequence of messages exchanged by the processing nodes, and message formats of the messages exchanged by the processing nodes. The example embodiment may also involve compiling the blueprint files into machine executable code. The machine executable code may be capable of: representing the processing nodes as decomposed, dynamically invoked units of logic, and transmitting the sequence of messages between the units of logic in accordance with the message formats. The units of logic may include a respective controller and one or more respective workers for each type of processing node.

Optimizing program parameters in multithreaded programming may include: generating, for a program, a plurality of low-level metric functions, each of the low-level metric functions calculating a respective low-level metric of a plurality of low-level metrics; generating one or more high-level metric functions for one or more high-level metrics, each of the one or more high-level metric functions comprising a piecewise-rational function based on one or more of the low-level metric functions; and generate, based on the one or more high level-metric functions, one or more data parameter values and one or more hardware parameter values, one or more program parameter values for executing the program, wherein the one or more program parameter values are configured to optimize the one or more high-level metrics.

A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and processing computational graphs that represent dynamically structured machine learning models are disclosed. An example system receives data identifying a plurality of operations that can be performed on input data for processing by a dynamically structured machine learning model. The system also receives a plurality of labels corresponding to arguments for the plurality of operations. A directed computational graph representing a comprehensive layer of the dynamically structured machine learning model is generated from the identified operations and labels. An example system then receives an input for processing by the machine learning model and specifies data flow through the directed computational graph.

In one embodiment, a method may receive, by a compiler of a host computing system, source code for a computer application. The method may also include separating a first portion of the source code and a second portion of the source code that are to be compiled for execution by an accelerator operatively coupled to the host computing system. The method may also include compiling the first portion of the source code to generate hardware description language code. A logic block is to be generated on the accelerator in view of the hardware description language code. The method also includes compiling the second portion of the source code to generate softcore processor code, and adding instructions to the softcore processor code to cause the softcore processor code to interact with the logic block during execution of the softcore processor code and the logic block.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Improvements in the placement of explicit preemption points into compiled code are disclosed. A control flow graph is created, from executable code, that includes every control path in a function. From the control flow graph, an estimated execution time for each control path is determined. For each control path, it is determined whether an estimated execution time of a control path exceeds a preemption latency parameter, wherein the preemption latency parameter is a maximum allowable time between preemption points. When it is determined that the estimated execution time of a particular control path violates the preemption latency parameter, an explicit preemption point is placed into the executable code that satisfies the preemption latency parameter.

An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

Annotations can be placed in source code to indicate properties for user-defined functions. A wide variety of properties can be implemented to provide information that can be leveraged when constructing a query execution plan for the user-defined function and associated core database relational operations. A flexible range of permitted partition arrangements can be specified via the annotations. Other supported properties include expected sorting and grouping arrangements, ensured post-conditions, and behavior of the user-defined function.